Apparatus and method for controlling an output buffer in a Hybrid Automatic Repeat Request (HARQ) mobile communication system

ABSTRACT

A mobile station apparatus and method provide for receiving packet data transmitted over a packet data channel, decoding the received packet data and delivering the decoded packet data to an upper layer in a mobile communication system transmitting packet data transmitted over a forward packet data channel and transmitting, over a forward packet data control channel, demodulation and decoding information of packet data transmitted over the forward packet data channel. The apparatus and method comprise a fast turbo decoder for decoding packet data received over the packet data channel depending on information received over the forward packet data control channel, storing the decoded data, and outputting buffer information of the stored data; an output buffer for storing the received packet data, and outputting the packet data upon receiving a read request. The apparatus and method further comprise an output buffer controller for receiving information on the decoded data and the buffer information from the fast turbo decoder, and generating an interrupt signal and a read address for reading data stored in the output buffer using the received data information and buffer information; and a processor for reading data stored in the output buffer according to the read address upon receiving the interrupt signal from the output buffer controller.

PRIORITY

[0001] This application claims priority under 350 U.S.C. § 119 to anapplication entitled “Apparatus and Method for Controlling Output Bufferin a HARQ Mobile Communication System” filed in the Korean IntellectualProperty Office on Jan. 7, 2003 and assigned Serial No. 2003-894, thecontents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to an apparatus andmethod for controlling a buffer in a mobile communication system, and inparticular, to an apparatus and method for controlling a buffer in amobile communication system using a Hybrid Automatic Repeat Request(hereinafter referred to as “HARQ”) scheme.

[0004] 2. Description of the Related Art

[0005] Mobile communication systems have been developed to provide ahigh-quality call service to moving users. With the development ofmobile communication systems, research is being conducted on a methodfor transmitting increasing amounts of data to users. In addition,mobile communication systems have already been switched from an analogsystem to a digital system. Using the digital system, the mobilecommunication systems can now transmit increased amounts of data tousers at higher speeds.

[0006] Generally, in digital mobile communication systems where avariation in channel condition is significant and different types ofservice traffic channels coexist with each other, a Hybrid AutomaticRepeat Request (hereinafter referred to as “HARQ”) scheme is used tomeet demand for high-speed data transmission, i.e., to increasetransmission throughput. Particularly, as commercialization ofhigh-speed data transmission service is realized, analysis and researchare actively performed for efficiently applying a HARQ scheme usingerror correction codes with a variable code rate, rather than a HARQscheme using existing error correction codes with a fixed code rate. Fora channel structure for high-speed transmission, a method of usinghigh-level modulation such as 8-ary phase shift keying (8-PSK) and16-ary quadrature amplitude modulation (16-QAM) beside the generalbinary phase shift keying (BPSK) or quadrature phase shift keying(QPSK), as a modulation scheme, is also taken into consideration.

[0007] Currently, a Code Division Multiple Access 2000 (CDMA2000) FirstEvolution Data and Voice (1x EV-DV) system, which is a new transmissionstandard of a synchronous Third Generation Partnership Project (3GPP2)CDMA system, has adopted a coding scheme using quasi-complementary turbocodes (QCTC) as its standard. The quasi-complementary turbo codesprovide a variable code rate to a coding scheme for a HARQ scheme over ahigh-speed data connection and provide improvement in soft combiningperformance using HARQ. In the 1x EV-DV system, packet datatransmission/reception is performed by an HARQ or fast HARQ operation ofa physical layer. This will be described in detail with reference toFIGS. 1 and 2.

[0008]FIG. 1 is a block diagram illustrating a relationship between anupper layer and a physical layer for ARQ processing according to theprior art. Referring to FIG. 1, a physical layer 110 decodes datareceived over a radio channel and provides decoded frame data. Thephysical layer 110 delivers the decoded frame data to a MAC layer 120which is an upper layer. The MAC layer 120 determines whether thedecoded frame data received from the physical layer 110 has a ProtocolData Unit (MuxPDU) error. When an error occurs, the MAC layer 120retransmits the defective data. However, when no error occurs, the MAClayer 120 transmits a new frame. When processing is performed in the MAClayer 120, since data decoded in the physical layer must be delivered tothe upper layer to be processed, ARQ processing speed is undesirablydecreased. In addition, since high-speed data process must be performed,a load on the MAC layer 120 is increased. Hence, there have beenproposed methods in which an operation performed in the upper layer isperformed in the physical layer. Such methods provide a structure inwhich an operation in the physical layer, i.e., hardware, is performedin the same way as an operation in software. In this context, if part ofthe operation of FIG. 1 is applied to the physical layer, a structurefor processing part of an ARQ operation in the physical layer isprovided as illustrated in FIG. 2.

[0009]FIG. 2 is a block diagram illustrating a relationship between anupper layer and a physical layer for improved fast (physical) HARQprocessing. With reference to FIG. 2, a description will now be made ofa relationship between an upper layer and a physical layer for improvedfast HARQ processing. A structure of FIG. 2 is realized when thestructure of FIG. 1 is performed in the physical layer. It should benoted that such a structure has never been proposed up to now. In otherwords, it should be noted that the concept of FIG. 2 is expected byapplying currently proposed methods, this has never been actuallyimplemented, and no discussion has been made on the operations that willbe described in the detailed description section below.

[0010] In FIG. 2, part of an ARQ operation that has been performed in aMAC layer 230 is performed in a physical layer or its intermediatelayer, for fast ARQ response and processing. That is, in this scheme, aphysical layer 200 has a basic physical layer 210 performing the sameoperation as that of FIG. 1, and an HARQ controller 220. The HARQcontroller 220 performs part of the operation that was performed in theconventional MAC layer. Therefore, the HARQ controller 220 is includedin the physical layer in structure, but performs part of an operation ofthe MAC layer 230. Because of such characteristics, the HARQ controller220 is often classified as a MAC layer. However, since the physicallayer determines data retransmission, a processing time for the samedata is shortened.

[0011] In addition, NAK transmission in the upper layer cannot performsoft combining for the same data, because the physical layer canmaintain a soft combined value for each symbol. However, since datasymbols delivered from the physical layer to the MAC layer are allexpressed with a binary value (0 or 1), although a symbol is repeated byretransmission, there is no way to soft combine the repeated symbol. Theonly method is a majority voting method for calculating the number of 0sand 1s for symbols having a binary value, and comparing the number of 0swith the number of 1s to decide a majority symbol. However, this methodalso cannot be used in the upper layer because of its requiredcalculations. On the contrary, NAK transmission in the physical layerenables soft combining of code symbols for the same encoder packet,contributing to efficient utilization of channel resources. Therefore,it is preferable to locate the HARQ controller 220 under a multiplexingsublayer 230 of the MAC layer. That is, it is preferable for the MAClayer to perform an operation of the physical layer.

[0012] This structure has a fast processing time compared with aconventional ARQ control method operating based on a radio link protocol(RLP). This will now be compared with the existing method. In theconventional method of FIG. 1, a NAK signal is received from one packettransmission, and a round trip delay of a minimum of about 200 msecoccurs up to a time when a retransmission packet is transmitted due tothe NAK signal. On the contrary, in the method of FIG. 2, HARQ generatesa very short round trip delay of a minimum of about severalmilliseconds. Therefore, it has a very good structure for implementingadaptive modulation and coding (AMC).

[0013] In order to actually operate HARQ with the structure of the upperlayer and the physical layer of FIGS. 1 and 2, a retransmission protocolof a transmitter for a retransmission request (i.e., NAK transmittedfrom a receiver) is required. For this, the 3GPP2 CDMA2000 1x systemuses Asynchronous and Adaptive Increment Redundancy (AAIR), and thiswill be described below.

[0014] A base station asynchronously performs packet transmission to acorresponding mobile station according to the quality of a forwardchannel. At this point, a modulation scheme and a code rate of thetransmission packet are adaptively applied according to a channelcondition. In addition, a packet transmission failure during initialtransmission is retransmitted, and during retransmission, a code symbolpattern that is different from that at the initial transmission can betransmitted. Such an AAIR retransmission scheme increases asignal-to-noise ratio (SNR) of packet data due to an increase in thenumber of retransmissions, and increases a coding gain due to a decreasein a code rate, thereby improving transmission/reception performance ofpacket data.

[0015] A channel used for transmission of forward packet data in the 1xEV-DV system includes a forward packet data channel (F-PDCH) for payloadtraffic and a forward packet data control channel (F-PDCCH) forcontrolling the F-PDCH. F-PDCH is a channel for transmitting an encoderpacket (EP) which is a transmission data block, and a maximum of up to 2channels are used to simultaneously transmit their encoder packets to 2mobile stations by time division multiplexing (TDM)/code divisionmultiplexing (CDM). An encoder packet is encoded by a turbo encoder, andthen divided into 4 subpackets having different Increment Redundancy(IR) patterns by OCTC symbol selection. The subpacket is a transmissionunit for initial transmission and retransmission, and at eachtransmission, an IR pattern of a subpacket is identified by a subpacketidentifier (SPID). A modulation scheme (QPSK, 8PSK or 16QAM) and atransmission slot length (1, 2 or 4 slots) of the subpacket aredetermined according to forward channel quality information transmittedfrom a mobile station and resources (the number of Walsh codes and powerassignable to F-PDCH) of a base station.

[0016] Information related to demodulation and decoding of F-PDCH ismultiplexed with F-PDCH through other orthogonal channels for the sameslot period, and then transmitted over the F-PDCCH which is a controlchannel. Information included in the F-PDCCH is very important forperforming a physical layer's HARQ operation by a mobile station, andrequires the following:

[0017] 1) fragmented Walsh code information available for F-PDCH everyseveral tens to several hundreds milliseconds;

[0018] 2) MAC_ID: MAC_ID of a mobile station (MS) to which F-PDCH isassigned;

[0019] 3) ACID: ID for identifying 4 ARQ channels (ARQ channel ID);

[0020] 4) SPID: ID for identifying an IR pattern of a subpacket;

[0021] 5) EP_NEW: information for distinguishing two consecutive encoderpackets in the same ARQ channel;

[0022] 6) EP_SIZE: a bit size of an encoder packet; and

[0023] 7) LWCI (Last Walsh Code Index): information on a Walsh code usedfor F-PDCH.

[0024] Meanwhile, packet data reception in a mobile station is performedby decoding the F-PDCCH. A mobile station first decodes F-PDCCH todetermine whether its own packet is being transmitted, and if it isdetermined that the transmitted packet is its own packet, the mobilestation performs demodulation and decoding on F-PDCH. If a currentlyreceived subpacket is a subpacket that was retransmitted for apreviously received encoder packet, the mobile station performs decodingby code-combining the currently received subpacket with code symbols ofan encoder packet that was previously received and stored therein. Ifthe decoding is successful, the mobile station transmits an ACK signalover a reverse ACK/NAK transmission channel (R-ACKCH), allowing the basestation to transmit the next encoder packet. If the decoding is notsuccessful, the mobile station transmits a NAK signal, requesting thebase station to retransmit the same encoder packet.

[0025] A unit for which a physical layer's HARQ operation is performedon one encoder packet is called an “ARQ channel.” In the CDMA2000 1xEV-DV system, a maximum of 4 ARQ channels can simultaneously operate,and these are called “N=4 fast HARQ channels.”

[0026] In the 1x EV-DV standard, it is provided that ACK/NAK_DELAYnecessary for performing by a mobile station a packet receptionoperation and transmitting ACK/NAK and the number of simultaneouslyavailable ARQ channels should be provided to a base station by themobile station, and this becomes an implementation issue for a mobilestation. Therefore, a possible ACK/NAK_DELAY supported by the mobilestation is 1 slot (=1.25 msec) or 2 slots (2.5 msec), and the possiblenumber of ARQ channels is 2, 3 or 4. With reference to FIGS. 3 and 4, adescription will now be made of an operation depending on ACK/NAK_DELAYand the number of ARQ channels.

[0027]FIG. 3 is a timing diagram between a base station and a mobilestation for ACK/NAK_DELAY=1 slot in HARQ in a mobile communicationsystem, and FIG. 4 is a timing diagram between a base station and amobile station for ACK/NAK_DELAY=2 slots in HARQ in a mobilecommunication system.

[0028] It will be assumed in FIGS. 3 and 4 that a forward packet datachannel (F-PDCH) is assigned to a mobile station A. In addition, for theconvenience of explanation, indexes are sequentially assigned to timeslots of both a base station (BS) and a mobile station (MS) from 0^(th)time slot beginning at a particular time. Further, in FIGS. 3 and 4,A(x,y) has the following meaning. Hatched parts refers to data to betransmitted to the mobile station A. In addition, ‘x’ refers to an ARQchannel, and ‘y’ refers to an index for distinguishing an IR pattern forthe same encoder packet. Based on this, a description will now be madeof FIG. 3 in which ACK/NAK_DELAY is 1 slot.

[0029] Referring to FIG. 3, data from a base station is transmitted to amobile station A at a 0^(th) slot. Then, the mobile station A receivesthe packet data at the same slot. In FIGS. 3 and 4, the base station andthe mobile station have different slot start points due to transmissiondelay occurring between the mobile station and the base station on thebasis of an absolute time. At this point, the base station transmitspacket data and a packet data control signal over a forward packet datachannel (F-PDCH) and a forward packet data control channel (F-PDCCH),respectively. Then, the mobile station A determines whether the data hasan error, for a one-slot processing time, and thereafter, transmits ACKor NAK to the base station. The “processing time” refers to a timerequired for performing demodulation and decoding on received packetdata for one slot, and transmitting the result at the next slot over areverse channel (R-ACKCH). For example, in FIG. 3, NAK is transmitted.The base station then receives the NAK at a 3^(rd) slot, and schedulesretransmission of the defective data at a 4^(th) slot. Thereafter, thebase station transmits data of a different pattern for the same encoderpacket according to the scheduling result.

[0030] Next, a description will be made of FIG. 4 in which ACK/NAK_DELAYis 2 slots. It will be assumed in FIG. 4 that an error has occurred in afirst data packet among the data packets transmitted from a base stationto a mobile station A, and the description will be focused on the firstdata packet. Since the delay time is 2 slots, the base stationcontinuously transmits packet data to the mobile station A at a 0^(th)slot, a 1^(st) slot and a 2^(nd) slot. The mobile station then checks anerror of the data transmitted at the 0^(th) slot for a period of the1^(st) to the 2^(nd) slots, checks an error of the data transmitted atthe 1^(st) slot for a period of the 2^(nd) to 3^(rd) slots, and checksan error of the data transmitted at the 2^(nd) slot for a period of the3^(rd) to 4^(th) slots. ACK/NAK for the data received at the 0^(th) slotis transmitted at the 3^(rd) slot, ACK/NAK for the data received at the1^(st) slot is transmitted at the 4^(th) slot, and ACK/NAK for the datareceived at the 2^(nd) slot is transmitted at a 5^(th) slot. If the basestation receives, at the 4^(th) slot, NAK for the packet datatransmitted at the 0^(th) slot, the base station performs, at the nextslot, retransmission on an encoder packet transmitted at the 0^(th)slot. The retransmitted packet data is the same packet as the previouslytransmitted packet but has a different IR pattern.

[0031] As can be understood from FIGS. 3 and 4, the mobile stationperforms synchronous ACK/NAK transmission in which the mobile stationmust transmit ACK or NAK for a received packet after a lapse of 1 slotor 2 slots. The base station performs asynchronous ACK/NAK transmissionin which the base station can transmit a packet at any slot afterreceiving ACK/NAK for a packet previously transmitted by the mobilestation for the same ARQ channel.

[0032] In addition, FIGS. 3 and 4 illustrate a 1-channel ARQ operationand a 4-channel ARQ operation, respectively. In the 1-channel ARQoperation of FIG. 3, data transmission to one mobile station uses only apart of base station resources, decreasing a packet data rate of acorresponding mobile station. In contrast, in the 4-channel ARQoperation of FIG. 4, one mobile station can use the entire resources ofthe base station, so a corresponding mobile station can obtain a maximumpacket data rate.

[0033] As illustrated in FIG. 4, upon receiving packets A(0,0), A(1,1)and A(2,0), a receiver soft-combines these packets before decoding ordecodes the received packets without soft combining. The receiverperforms cyclic redundancy check (CRC) to determine whether an error hasoccurred in the decoded data, and transmits ACK/NAK over a reversechannel according to the CRC result. Such an operation can be performedevery 1.25 msec.

[0034] However, in a 1x EV-DV system for a high-speed data service, anarchitecture between a host (or CPU) and an output buffer for decoding areceived packet and transmitting the decoded packet to the host can alsobecome an important design factor. This is because in the 1x EV-DVhigh-speed data service system, a transmission time of a packet, a kindof a transmission frame, is as short as about 1.25 msec, whereas thenumber of bits included in one packet is greatly increased to severalthousands of bits. This means a large increase in a channel decodingtime required for decoding one packet. Therefore, an abrupt decrease ina time assignable for data transmission out of the processing timeassigned to the receiver occurs. In addition, due to inconsistency oforders caused by retransmission, even an error-free transmission packetreceived successfully can lack continuity because of discrepancy in adecoding time. That is, received packets may be discontinuous, losingtheir continuity.

[0035] Generally, a current medium- and low-speed data system uses suchdecoders as a turbo decoder or a Viterbi decoder as a channel decoder.In such a system, a single output buffer or a double output buffer hasbeen used in order to transmit data from a decoder to a host. However,as high-speed data service for the 1x EV-DV system becomes popular, theexisting output buffer's structure has the following problems. If thefollowing problems cannot be solved, a host having the existingprocessing capability must assign most of its processing capability fordata transmission. Therefore, the host cannot perform processingfunctions of other adjacent blocks and its upper protocol. In addition,if a very fast host is adopted to solve such problems, unnecessary powerconsumption may occur for other functions except the data transmission.A detailed description will now be made of the problems which may occurwhen a high-speed data service is processed with the current system.

[0036] (1) Currently, in most systems, when a channel decoder transmitsdata to a host, data transmission from the channel decoder to the hostis controlled by the channel decoder. Therefore, the channel decoder isdesigned to send the host an interrupt for data transmission uponcompletion of decoding. In the case of a low-speed data processingsystem, a buffer storing data has a single buffer structure. Inaddition, the system assigns part of the entire processing time givenfor decoding as a time for data transmission, and completes transmissionof all data during the assigned time period. However, an increase in adata rate causes an increase in a decoding time. Therefore, such asingle buffer structure transmitting data using part of the entireprocessing time given for decoding can no longer be used.

[0037] (2) In a low-speed system or a system requiring faster dataprocessing than the low-speed system, a double buffer structure is usedin order to solve the above problems. The double buffer structureprovides a method for extending a decoding time and a data transferringtime by alternately designating two buffers to read/write modes. In thismethod, an interval at which an interrupt for data transmission occursis relatively long. Thus, from the viewpoint of the host, this method isefficient when a large volume of data is transmitted by one interrupt.However, in the 1x EV-DV system supporting a high-speed data service,most decoding frames have a very short time, whereas the number of bitsincluded in a corresponding decoding frame is very highly increased.Therefore, although such a method is used, excessive data transmissionburden is imposed on the host due to frequent occurrence of theinterrupt, so the host may not perform its unique tasks.

[0038] (3) In addition, the 1x EV-DV system supporting a high-speed dataservice uses a variable processing time mode by including a channeldecoder in order to reduce a processing burden on a receiver. The 1xEV-DV system identifies the variable processing time mode usingACK_DELAY, and a mobile station can be assigned a processing time of 1slot (1.25 msec) or 2 slots (2.5 msec) according to a value ofACK_DELAY. Under this condition, it is efficient that an output bufferstructure of the receiver has a structure that adaptively operatesaccording to a processing time mode. However, since the existing systemsuse only one fixed processing time mode, they cannot be adaptively usedaccording to ACK_DELAY.

[0039] (4) Furthermore, most of the current systems use a channelsupporting a circuit mode service. Therefore, the current system doesnot support physical layer HARQ, and its receiver does not use softcombining due to retransmission. Thus, an identifier (ID) of a decodedframe decoded by a channel decoder is not required. However, the 1xEV-DV high-speed data service system supports a pure packet mode.Therefore, a reception time and a decoding-completed time of each packetmay be in discord with transmission order of the corresponding packet.Thus, there is a demand for an apparatus for solving such problems.

SUMMARY OF THE INVENTION

[0040] It is, therefore, an object of the present invention to providean output buffer control apparatus and method for transmitting datadecoded by a channel decoder while reducing a load on a processor in ahigh-speed data service system.

[0041] It is another object of the present invention to provide anoutput buffer control apparatus and method for securing a decoding timeof a channel decoder in a high-speed data service system.

[0042] It is further another object of the present invention to providean output buffer control apparatus and method for deliveringchannel-decoded data to a processor irrespective of an acknowledgementdelay time ACK_DELAY_TIME in a high-speed data service system.

[0043] It is yet another object of the preset invention to provide anoutput buffer control apparatus and method for preventing wrong errordetection caused by discontinuity of packet data retransmitted based onHybrid Automatic Repeat Request (HARQ) in a high-speed data servicesystem.

[0044] It is still another object of the present invention to provide anoutput buffer control apparatus and method for enabling fast response toreceived packet data in a high-speed data service system.

[0045] To substantially achieve the above and other objects, a mobilestation apparatus provides for receiving packet data transmitted over apacket data channel, decoding the received packet data and deliveringthe decoded packet data to an upper layer in a mobile communicationsystem transmitting packet data transmitted over a forward packet datachannel and transmitting, over a forward packet data control channel,demodulation and decoding information of packet data transmitted overthe forward packet data channel. The apparatus comprises a fast turbodecoder for decoding packet data received over the packet data channeldepending on information received over the forward packet data controlchannel, storing the decoded data, and outputting buffer information ofthe stored data; an output buffer for storing the received packet data,and outputting the packet data upon receiving a read request. Theapparatus further comprises an output buffer controller for receivinginformation on the decoded data and the buffer information from the fastturbo decoder, and generating an interrupt signal and a read address forreading data stored in the output buffer using the received datainformation and buffer information; and a processor for reading datastored in the output buffer according to the read address upon receivingthe interrupt signal from the output buffer controller.

[0046] Preferably, the output buffer comprises a dualized area forstoring the decoded data, and when data is read from one area of theoutput buffer, the fast turbo decoder decodes the read data and storesthe decoded data in another area after completion of decoding.

[0047] Preferably, the buffer information includes area information andaddress information of the buffer where the decoded data is stored, andthe decoded data information includes at least one of error informationof the decoded data, status information of the decoder, anddecoding-done information.

[0048] Preferably, the output buffer controller comprises a page bufferselector for receiving a system time signal of a receiver, selecting oneof the dualized buffers according to a 1-slot delay response mode, andselecting a given page of the selected buffer; a stop position selectorfor receiving the system time signal and a decoding clock, andgenerating a stop position signal that can be randomly set in one slot;a flag generator being cleared according to the system time of thereceiver, for outputting a flag according to a turbo decoder enablesignal of the packet data; a buffer selector for receiving a signal ofthe flag generator, an output signal of the stop position selector, andthe turbo decoder enable signal, and selecting one of the dualizedbuffers according to a 2-slot delay response mode; a page selector forselecting a page of the selected buffer according to the 2-slot delayresponse mode; and an interrupt controller for generating an interruptsignal by receiving signals from the page buffer selector, the bufferselector and the page selector, and buffer status signals from thedualized buffers.

[0049] Preferably, the output buffer controller is included in a HybridAutomatic Repeat Request (HARQ) controller located in a physical layer.

[0050] Preferably, the decoded data information includes at least one oferror information of the decoded data, status information of thedecoder, and decoding-done information.

[0051] Preferably, the output buffer controller generates an interruptsignal and a read address for data reading, when at least two datapackets are received.

[0052] To substantially achieve the above and other objects, a methodprovides for delivering decoded data to an upper layer in a mobilestation apparatus including a decoder for decoding received packet data,a dualized output buffer for storing the decoded data and an outputbuffer controller for delivering data stored in the output buffer to theupper layer in a mobile communication system transmitting packet datatransmitted over a forward packet data channel and transmitting, over aforward packet data control channel, demodulation and decodinginformation of packet data transmitted over the forward packet datachannel. The method comprises the steps of receiving decoded datainformation and buffer information from the decoder; generating aninterrupt signal and output buffer information for delivering thedecoded data to the upper layer if a predetermined time has passed; andstopping interrupt if data transmission to the upper layer is completed.

[0053] Preferably, the buffer information includes area information andaddress information of the buffer where the decoded data is stored, andthe decoded data information includes at least one of error informationof the decoded data, status information of the decoder, anddecoding-done information.

[0054] To substantially achieve the above and other objects, a methodprovides for delivering decoded data to an upper layer in a mobilestation apparatus including a decoder for decoding received packet data,a dualized output buffer for storing the decoded data, and an outputbuffer controller for delivering data stored in the output buffer to theupper layer in a mobile communication system transmitting packet datatransmitted over a forward packet data channel and transmitting, over aforward packet data control channel, demodulation and decodinginformation of packet data transmitted over the forward packet datachannel. The method comprises the steps of receiving decoded datainformation and buffer information from the decoder; generating aninterrupt signal and output buffer information for delivering thedecoded data to the upper layer if a predetermined number of data blocksare decoded by the decoder and stored in the output buffer; and stoppinginterrupt if data transmission to the upper layer is completed.

[0055] Preferably, the buffer information includes area information andaddress information of the buffer where the decoded data is stored, andthe decoded data information includes at least one of error informationof the decoded data, status information of the decoder, anddecoding-done information.

[0056] Further, the method comprises the steps of: generating outputbuffer information and an interrupt signal for delivering the decodeddata to the upper layer if no packet data is received over the packetdata channel within a predetermined time; and stopping interrupt if datatransmission to the upper layer is completed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The above and other objects, features and advantages of thepresent invention will become more apparent from the following detaileddescription when taken in conjunction with the accompanying drawings inwhich:

[0058]FIG. 1 is a block diagram illustrating a relationship between anupper layer and a physical layer for Automatic Repeat Request (ARQ)processing according to the prior art;

[0059]FIG. 2 is a block diagram illustrating a relationship between anupper layer and a physical layer for improved fast (physical) HybridAutomatic Repeat Request (HARQ) processing;

[0060]FIG. 3 is a timing diagram illustrating a relationship between abase station and a mobile station for ACK/NAK_DELAY=1 slot in HARQ in amobile communication system;

[0061]FIG. 4 is a timing diagram illustrating a relationship between abase station and a mobile station for ACK/NAK_DELAY=2 slots in HARQ in amobile communication system;

[0062]FIG. 5 is a block diagram illustrating the connection between anHARQ controller, an output buffer controller, and an output bufferaccording to an embodiment of the present invention;

[0063]FIG. 6 is a timing diagram for possible cases where the turbodecoding-done signal PDCH_TURBO_DONE follows the turbo decoder enablesignal PDCH_TURBO_EN, according to an embodiment of the presentinvention;

[0064]FIG. 7 is a timing diagram illustrating examples of ademodulation-done signal PDCH_DEMOD_DONE and a turbo decoder enablesignal PDCH_TURBO_EN being output, according to an embodiment of thepresent invention;

[0065]FIG. 8 is an example of a timing diagram between a turbodecoding-done signal PDCH_TURBO_DONE and its consecutive turbo decoderenable signal PDCH_TURBO_EN according to an embodiment of the presentinvention;

[0066]FIG. 9 is a simplified block diagram illustrating a structure ofan output buffer according to an embodiment of the present invention;

[0067]FIG. 10 is a detailed block diagram illustrating a structure of anoutput buffer controller according to an embodiment of the presentinvention;

[0068]FIG. 11 is a block diagram illustrating a detailed structure ofthe page/buffer selector according to an embodiment of the presentinvention;

[0069]FIG. 12 is a block diagram illustrating a detailed structure ofthe buffer selector according to an embodiment of the present invention;

[0070]FIG. 13 is a block diagram illustrating a detailed structure ofthe interrupt controller according to an embodiment of the presentinvention;

[0071]FIG. 14 is a timing diagram of signals output from the outputbuffer controller in a 1-slot ACK/NAK_DELAY mode according to anembodiment of the present invention;

[0072]FIG. 15 is a timing diagram illustrating an example in which thesum of a decoding time of a fast turbo decoder and a data transferringtime is limited to 2.5 msec in a 1-slot ACK/NAK_DELAY mode according toan embodiment of the present invention;

[0073]FIGS. 16 and 17 are timing diagrams of an output buffer in a fastturbo decoder in a 2-slot ACK/NAK_DELAY mode according to an embodimentof the present invention;

[0074]FIG. 18 is a timing diagram illustrating examples of controltimings of an output buffer and operations of a fast turbo decoder in a1-slot ACK/NAK_DELAY mode and a 2-slot ACK/NAK_DELAY mode according toan embodiment of the present invention;

[0075]FIG. 19 is a diagram illustrating operational timing between theprocessor, the HARQ controller and the fast turbo decoder in a 1-slotACK/NAK_DELAY mode according to an embodiment of the present invention;

[0076]FIG. 20 is a diagram illustrating operational timing between theprocessor, the HARQ controller and the fast turbo decoder in a 2-slotACK/NAK_DELAY mode according to an embodiment of the present invention;and

[0077]FIG. 21 is a flowchart illustrating an entire control operationperformed by the output buffer controller according to an embodiment ofthe present invention.

[0078]FIG. 22 is a block diagram illustrating a mobile station includingan output buffer controller according to an embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0079] An embodiment of the present invention will now be described indetail with reference to the accompanying drawings. In the drawings, thesame or similar elements are denoted by the same reference numerals. Inthe following description, a detailed description of known functions andconfigurations incorporated herein has been omitted for conciseness.

[0080] A system according to the present invention will now be describedin detail, compared with the current available technology.

[0081] First, most available systems hold a structure in which an outputbuffer is included in a channel decoder (e.g., turbo decoder or aViterbi decoder), and a host transmits data in the buffer using anaddress bus and a data bus. That is, in the currently available system,the channel decoder generates an interrupt directly to the host when itdesires to transmit data in the output buffer to the host. However, inthe embodiment of the present invention, an output buffer controller(OBUFC) delivers an interrupt for data transmission to the host, fortransmission of data in the channel decoder. The output buffercontroller receives a signal indicating completed decoding from thechannel decoder through, for example, interrupt, signaling, or flag.Based on a value of this signal and output buffer's status informationstored in the output buffer controller, if it is determined that datatransmission is necessary, the output buffer controller sends the hostan interrupt for data transmission.

[0082] Second, the output buffer controller has two available newinterface structures in order to generate an interrupt to the host.

[0083] A first interface is an interface between the output buffercontroller and the channel decoder. The interface between the outputbuffer controller and the channel decoder sends the channel decoderaddress generation information for determining a storage position of theoutput buffer where data completely decoded by the channel decoder is tobe stored. In addition, the interface between the output buffercontroller and the channel decoder sends the output buffer controller aninterrupt, signaling or flag indicating that decoding is completed inthe channel decoder.

[0084] Another interface is an interface between the output buffercontroller and the host. The interface between the output buffercontroller and the host sends the host data stored in the output buffer.Therefore, the interface between the output buffer controller and thehost sends the following information in order to deliver data decoded bythe channel decoder from the output buffer controller to the host.First, the interface sends address information indicating a positionwhere the channel-decoded data is stored in the output buffer. Second,the interface sends information related to the channel-decoded data, forexample, size, type and time of a frame. Third, the interface sends aninterrupt requesting transmission of data stored in the output buffer.In addition, the interface between the output buffer controller and thehost sends signaling or flag indicating completed transmission of datain the output buffer, from the host to the output buffer controller.

[0085] Third, the channel decoder includes an output buffer capable ofstoring a plurality of decoded data frames. In the currently availablesystem, the channel decoder includes an output buffer for storing onedecoded frame. However, in the embodiment of the present invention, thechannel decoder is designed to have a plurality of output buffer spaces.A maximum size of the output buffer included in the channel decoder isdetermined according to a size of a decoded frame which is a data blockoutput from the channel decoder, and the maximum number of accumulateddecoded frames, requested by the host. In addition, the output bufferincluded in the channel decoder has a double buffer structure. The thedouble buffer structure is used to enable the channel decoder to securea maximum decoding time, and secure a maximum available time for datatransmission to the host.

[0086] Fourth, the output buffer is designed to operate in a dual modein order to support both of two modes of ACK_DELAY provided in the 1xEV-DV system. That is, the output buffer has a structure supporting bothof the two modes with one circuit without design of a new circuit. Anoutput buffer controller based on ACK_DELAY is separately designed, andthis is integrated into one general output buffer controller. Inparticular, for ACK_DELAY=2 slots, a control signal for datatransmission is generated using an adaptive signal control method inorder to provide a maximum decoding time to the channel decoder.Therefore, variable data transmission interrupt timing control isavailable.

[0087] Fifth, the output buffer controller sends the host an interruptfor data transmission only when a decoded frame having no decoding errorexists in the output buffer of the channel decoder. Otherwise, theoutput buffer controller automatically checks “Empty Buffer” so as notto generate an interrupt. The reason for designing the output buffercontroller in this manner is as follows. Commonly, a host (or CPU)suffers from an initial delay for which a considerable number ofcommands are performed from a time when an interrupt for datatransmission is generated through a time when actual data transmissionis initiated. Such an overhead acts as a considerable load on aninterrupt process. Therefore, when there is no transmission data decodedwithout an error, the output buffer controller must not generate aninterrupt, thereby reducing a data processing burden on the host.

[0088] Sixth, the output buffer controller transmits a reception time ofeach decoded frame, e.g., system time SYS_TIME, to the host along withthe decoded data. Such reasons are as follows. The host sends decodeddata to the output buffer only when an interrupt is generated from theoutput buffer controller. That is, several frames decoded by the channeldecoder are accumulated and then transmitted to the host. The decodeddata delivered to the host has a timing gap between a time when actualchannel decoding is performed and a time when the data is transmitted tothe host. In the case of general service traffic, the timing gap isnegligible. However, when receiving a control message requesting a fastresponse, for example, channel setup and supervision messages, a host ofa mobile station requires reception time information. Therefore, theoutput buffer controller provides reception time information of eachdecoded frame taking such an occasion into consideration. In thismanner, the host can detect a reception time of each decoded frame usingthe received system time information. In addition, the host can transmitvarious parameters altogether required by an upper layer, observed in areceiver. For example, in a normal mode, the host transmits only theabove parameters, and in a test mode or an observation mode, the hostcan gather various parameters observed in the receiver and transmit thegathered parameters. Therefore, in the embodiment of the presentinvention, parameters delivered to the upper layer are not limited tothe above-stated parameters.

[0089] Similarly, in the Evolution Data and Voice (1x EV-DV) system, amaximum of 4 Automatic Repeat Request (ARQ) channels are used in series.Therefore, the host requires , a retransmission channel ID (ACID) whichis information for identifying an ARQ channel. As a result, the outputbuffer controller according to the embodiment of the present inventiontransmits ACID of each decoded frame to the host during datatransmission.

[0090]FIG. 5 is a block diagram illustrating the connection between aHybrid Automatic Repeat Request (HARQ) controller, an output buffercontroller, and an output buffer according to an embodiment of thepresent invention. The connection and operation of the output buffercontroller will now be described with reference to FIG. 5.

[0091] As illustrated in FIG. 5, an output buffer controller 300 isincluded in a HARQ controller 30. Actually, however, the output buffercontroller 300 may not be included in the HARQ controller 30. The reasonwhy the output buffer controller 300 is included in the HARQ controller30 is because it is assumed that the HARQ controller 30 has alreadyreceived a signal that the output buffer controller 300 requires. Forthe convenience of explanation, it will be herein assumed that theoutput buffer controller 300 is included in the HARQ controller 30. Inaddition to the output buffer controller 300, the HARQ controller 30includes therein a state part (not shown) for outputting a statetransition signal according to each operation mode, a state functionpart (not shown) for controlling an operation according to each state,and a register (not shown) for storing internally processed data orstoring a signal. In addition, the HARQ controller 30 receives a turbodecoding-done signal PDCH_TURBO_DONE of a packet data channel from afast turbo decoder 40. The turbo decoding-done signal of a packet datachannel is input to the HARQ controller 30 when the fast turbo decoder40 receives packet data from a packet data channel and completes turbodecoding of the received packet data. In this state, the fast turbodecoder 40 stores turbo-decoded data in an output buffer 400. Uponreceiving the turbo decoding-done signal of a packet data channel, theoutput buffer controller 300 in the HARQ controller 30 counts the turbodecoding-done signal of a packet data channel. If the count value islarger than a preset value, the output buffer controller 300 provides aprocessor (CPU or host) 50 with a signal for reading data stored in theoutput buffer 400 so that the processor 50 reads out the data stored inthe output buffer 400. Herein, the preset count value is set to a valueof 2 or above. The preset count value is set to a value of 2 or above toallow the processor 50 to read decoded packet data stored in the outputbuffer 400 by as many as two data blocks instead of reading the datastored in the output buffer 400 each time a packet is received. If theprocessor 50 reads data from the output buffer 400 each time decoding iscompleted, a load on the processor 50 is increased.

[0092] In the embodiment of the present invention, the output buffercontroller 300 provides the processor 50 with an interrupt requestingthe processor 50 to read the output buffer 400 when the turbodecoding-done signal of a packet data channel is received two or moretimes, by way of example. However, the number of the turbo decoding-donesignals received, at which an interrupt is to be generated, can be setto a different value according to an expected load of the processor 50.Alternatively, the output buffer controller 300 can generate aninterrupt by counting a preset time of, for example, 5 msec, in additionto setting the number of turbo decoding-done signals.

[0093] The fast turbo decoder 40 includes a dualized output buffer 400therein. The dualized output buffer 400 stores data turbo-decoded by thefast turbo decoder 40. A position where the data is stored is appointedbased on a control signal from the output buffer controller 300 includedin the HARQ controller 30.

[0094] The processor 50 reads data stored in the output buffer 400 inthe fast turbo decoder 40 in response to an interrupt received from theHARQ controller 30. The processor 50 can perform processing of amultiplexing (MUX) layer and a radio link protocol (RLP).

[0095] A description will now be made of input/output signals to andfrom the blocks illustrated in FIG. 5 and operations thereof. The HARQcontroller 30 must enable the fast turbo decoder 40 upon receiving dataover a packet data channel (PDCH). That is, the HARQ controller 30provides a turbo decoder enable signal PDCH_TURBO_EN to the fast turbodecoder 40 upon receiving data over the packet data channel. Further,the HARQ controller 30 delivers size information EP_SIZE_TURBO of anencoder packet received over the packet data channel to the fast turbodecoder 40. In response, the fast turbo decoder 40 can perform turbodecoding. The fast turbo decoder 40 provides a turbo decoding-donesignal PDCH_TURBO_DONE to the HARQ controller 30 when turbo decoding ofthe packet data channel PDCH is completed. In this manner, a decodingoperation is performed in the fast turbo decoder 40. The 1x EV-DV systemsupports both 1-slot ACK_DELAY and 2-slot ACK_DELAY. Therefore, theoutput buffer 400 and the HARQ controller 30 used in a high-speed dataservice modem can classify decoding and data transferring times into twocases as shown in Table 1 below. In Table 1, NOS stands for the “Numberof Slots” and denotes the number of slots occupied by one encoder packetfor transmission. TABLE 1 1-slot ACK_DELAY 2-slot ACK_DELAY NOS = 1 1.25msec + 1.25 msec 1.25 msec + 1.25 msec or 1.25 msec + 2.5 msec NOS = 22.50 msec + 1.25 msec 2.50 msec + 1.25 msec or 2.50 msec + 2.5 msec NOS= 3 5.00 msec + 1.25 msec 5.00 msec + 1.25 msec or 5.00 msec + 2.5 msec

[0096] In the case of 1-slot ACK_DELAY, demodulation and decoding ofdata received over a packet data channel should be completed within 1.25msec. However, in the case of 2-slot ACK_DELAY, demodulation anddecoding of data received over a packet data channel should be completedwithin 2.5 msec.

[0097] With reference to FIGS. 6 to 8, a description will now be made oftimings of the turbo decoder enable signal PDCH_TURBO_EN and the turbodecoding-done signal PDCH_TURBO_DONE. FIG. 6 is a timing diagramillustrating examples of the turbo decoding-done signal PDCH_TURBO_DONEfollowing the turbo decoder enable signal PDCH_TURBO_EN, according to anembodiment of the present invention.

[0098] A relation between the turbo decoder enable signal PDCH_TURBO_ENand the turbo decoding-done signal PDCH_TURBO_DONE illustrated in FIG. 6can be roughly divided into two cases as mentioned above: a first casecorresponds to 1-slot ACK_DELAY and a second case corresponds to 2-slotACK_DELAY. The first case is subdivided into two cases as illustrated inFIG. 6. In one case, a decoding time t_DEC falls within 1.25 msec. Thatis, a turbo decoding-done signal PDCH_TURBO_DONE is generated within 1slot after a turbo decoder enable signal PDCH_TURBO_EN is received fromthe HARQ controller 30. In this case, an encoder packet (EP) is small insize or a channel condition is good, so turbo decoding is rapidlycompleted in the turbo decoder 40 within the decoding time t_DEC of 1.25msec. In another case, a turbo decoding-done signal PDCH_TURBO_DONE isgenerated at a slot boundary. In this case, a channel condition is pooror an encoder packet is large in size, so a decoding time t_DEC becomeslong.

[0099] Even in the second case of 2-slot ACK_DELAY, if a channelcondition is good or an encoder packet is small enough in size, a turbodecoding-done signal PDCH_TURBO_DONE is generated within two slots.However, if a channel condition is poor or an encoder packet is verylarge in size, a turbo decoding-done signal PDCH_TURBO_DONE is generatedat a boundary of a second slot.

[0100]FIG. 7 is a timing diagram illustrating examples of ademodulation-done signal PDCH_DEMOD_DONE and a turbo decoder enablesignal PDCH_TURBO_EN being output, according to an embodiment of thepresent invention. With reference to FIG. 7, a description will now bemade of the demodulation-done signal PDCH_DEMOD_DONE and the turbodecoder enable signal PDCH_TURBO_EN generated according to an embodimentof the present invention.

[0101] In FIG. 7, a turbo decoder enable time t_GAP represents a timefor which a demodulation-done signal PDCH_DEMOD_DONE of data receivedover a packet data channel is output and the turbo decoder 40 is enabledin response to the demodulation-done signal PDCH_DEMOD_DONE. If the HARQcontroller 30 receives a demodulation-done signal PDCH_DEMOD_DONE from aPDCH demodulator, it means that an encoder packet to be decoded iswaiting in a corresponding slot. Therefore, a turbo decoder enablesignal PDCH_TURBO_EN must be set up in the corresponding slot. If theturbo decoder enable signal PDCH_TURBO_EN is received, the turbo decoder40 is enabled to decode data. Thus, the HARQ controller 30 must generatea turbo decoder enable signal PDCH_TURBO_EN at a slot where demodulationis completed. In an example of FIG. 7, a turbo decoder enable signalPDCH_TURBO_EN can be generated when demodulation is completed. In theworst case, the turbo decoder enable signal PDCH_TURBO_EN is output at aboundary of a 1.25-msec slot. Such a turbo decoder enable time t_GAP hasthe following 4 relationships.

[0102] (1) When a k^(th) turbo demodulation-done signal PDCH_DEMOD_DONEis generated at a particular slot, a k^(th) turbo decoder enable signalPDCH_TURBO_EN must be generated at the slot.

[0103] (2) The turbo decoder enable time t_GAP which is a time gapbetween the above two signals is always shorter than 1.25 msec.

[0104] (3) It is preferable to minimize the turbo decoder enable timet_GAP for 1-slot ACK_DELAY.

[0105] (4) For 2-slot ACK_DELAY, the turbo decoder enable time t_GAP isadaptively set according to a size EP_SIZE and a signal-to-interferenceratio (C/I) of an encoder packet.

[0106] The adaptive signal control of Case (4) occurs when a sizeEP_SIZE of a previous encoder packet is very large or a C/I of aprevious encoder packet is very low, so that the fast turbo decoder 40requires many iterations. To this end, a decision tale or algorithm thatconsiders a size EP_SIZE and a C/I of a previous encoder packet, and asize EP_SIZE and a C/I of a current encoder packet is required. The useof the decision table or algorithm can reduce occurrence of reverse NAK,contributing to an increase in throughput of a mobile station. In orderto set such a variable turbo decoder enable time t_GAP, the HARQcontroller 30 limits the number of possible positions for the turbodecoder enable signal PDCH_TURBO_EN to 16. Here, 16 is a parameterconsidered during design and is the maximum number of positions wherethe PDCH_TURBO_EN is set up. That is, it means the number of positionswhere the PDCH_TURBO_EN is generated, which can be artificially set inone slot by the HARQ controller 30. Therefore, if it is desirable to setpositions of the PDCH_TURBO_EN at very precise intervals, this value isset to a large value. In contrast, if precision of position setting isnot so high, this value is set to a small value. In the embodiment ofthe present invention, this value is set to 16, because it is believedthat with such precision, it is possible to sufficiently distinguishperformance differences of iterative decoding by the turbo decoder.However, this value can be replaced with 32 or 64 during design.

[0107] Even though the HARQ controller 30 uses more than 16 settingpositions, it is not practically possible to more precisely distinguishperformance differences of iterative decoding.

[0108]FIG. 8 is a timing diagram illustrating an example of arelationship between a turbo decoding-done signal PDCH_TURBO_DONE andits consecutive turbo decoder enable signal PDCH_TURBO_EN according toan embodiment of the present invention. With reference to FIG. 8, adescription will now be made of a function between the turbodecoding-done signal PDCH_TURBO_DONE and a turbo decoder enable signalPDCH_TURBO_EN.

[0109] As illustrated in FIG. 8, a relationship between a turbodecoding-done signal PDCH_TURBO_DONE and its consecutive turbo decoderenable signal PDCH_TURBO_EN can be roughly classified into two cases. Ina first case, the turbo decoding-done signal PDCH_TURBO_DONE and itsconsecutive turbo decoder enable signal PDCH_TURBO_EN are generated indifferent slots as shown by two upper waveforms in FIG. 8. In a secondcase, the turbo decoding-done signal PDCH_TURBO_DONE and its consecutiveturbo decoder enable signal PDCH_TURBO_EN are generated in the same slotas shown by the other 3 waveforms in FIG. 8.

[0110] The first case will now be described. In the first case, after ak^(th) turbo decoding-done signal PDCH_TURBO_DONE is generated in acurrent slot, a (k+1)^(th) turbo decoder enable signal PDCH_TURBO_EN isgenerated in the next slot. In this case, a size EP_SIZE of an encoderpacket is small or a channel condition is good. When a size EP_SIZE ofan encoder packet is small or a channel condition is good, the fastturbo decoder 40 can rapidly complete turbo decoding. Thus, the fastturbo decoder 40 waits to receive information on a size of an encoderpacket received from the HARQ controller 30 in the next slot. This isbecause if there is no information on a size of a new encoder packet,the fast turbo decoder 40 cannot perform decoding. The most extreme caseof a second upper case of FIG. 8, the turbo decoding-done signalPDCH_TURBO_DONE is generated at a boundary of a (k+1)^(th) slot.

[0111] Next, a description will be made of the second case in which theturbo decoding-done signal PDCH_TURBO_DONE and its consecutive turbodecoder enable signal PDCH_TURBO_EN are generated in the same slot. Thesecond case most frequently occurs in an actual apparatus. ForACK/NAK_DELAY=2 slots, the HARQ controller 30 sets a generation positionof a (k+1)^(th) turbo decoder enable signal DPCH_TURBO_EN to a rear partof the slot in order to artificially increase a turbo decoding time, andthis case also corresponds to the second case. In an extreme case, theHARQ controller 30 outputs a (k+1)^(th) turbo decoder enable signalPDCH_TURBO_EN and outputs a (k+1)^(th) turbo decoding-done signalPDCH_TURBO_DONE in the slot. In this case, the HARQ controller 30generates the turbo decoder enable signal PDCH_TURBO_EN in the nextslot. Accordingly, there is a case where there are three control signalstransmitted from the HARQ controller 30 to the fast turbo decoder 40within one slot. This case is shown by a fourth waveform of FIG. 8. Inthe case of the last waveform of FIG. 8, if the HARQ controller 30desires to artificially increase a turbo decoding time for 2-slotACK/NAK_DELAY, it sets a generation position of a (k+1)^(th) turbodecoder enable signal PDCH_TURBO_EN to a rear part of a (k+1)^(th) slotirrespective of whether a k^(th) turbo decoding-done signal is output ornot. In this case, the (k+1) turbo decoder enable signal PDCH_TURBO_ENis output at a boundary of the (k+1)^(th) slot after the fast turbodecoder 40 performs decoding.

[0112] The foregoing description made in connection with FIG. 8 can besummarized into the following two rules.

[0113] (1) If there are two consecutive encoder packets to be decoded, atime t_TB_GAP between a k^(th) turbo decoding-done signalPDCH_TURBO_DONE and a (k+1)^(th) turbo decoder enable signalPDCH_TURBO_EN is shorter than 1.25 msec in most cases as illustrated inFIG. 8.

[0114] (2) A k^(th) turbo decoding-done signal PDCH_TURBO_DONE, a(k+1)^(th) turbo decoder enable signal PDCH_TURBO_EN, and a (k+1)^(th)turbo decoding-done signal PDCH_TURBO_DONE can coexist in one slot.

[0115] A maximum decoding time and a data transferring time can bedetermined by combining FIGS. 6, 7 and 8. A description of the maximumdecoding time and the data transferring time will be made below.

[0116] For example, if a k^(th) demodulation-done signal PDCH_DEMOD_DONEis generated, a k^(th) turbo decoder enable signal PDCH_TURBO_EN must begenerated, and they exist within one slot. A maximum of 2 slots arerequired from a time when the k^(th) turbo decoder enable signalPDCH_TURBO_EN is generated to a time when the fast turbo decoder 40generates a k^(th) turbo decoding-done signal PDCH_TURBO_DONE inresponse to the k^(th) turbo decoder enable signal PDCH_TURBO_EN.Therefore, the total required time is equal to or shorter than 2 slots,i.e., 2.5 msec, from the slot where the k^(th) turbo demodulation-donesignal PDCH_DEMOD_DONE is generated. Possible cases occurring in thisperiod can be determined by combining FIGS. 6 and 7. Since a timerequired for new turbo decoding from the k^(th) turbo decoding-donesignal PDCH_TURBO_DONE becomes a minimum of 2 slots, a new turbo decoderenable signal PDCH_TURBO_EN can be generated within a maximum of 3 slotsfrom the k^(th) turbo decoder enable signal PDCH_TURBO_EN.

[0117] Next, a description will be made of a structure of an outputbuffer and an output buffer controller according to an embodiment of thepresent invention.

[0118]FIG. 9 is a simplified block diagram illustrating a structure ofan output buffer according to an embodiment of the present invention.Structure and operation of the output buffer according to the presentinvention will now be described in detail with reference to FIG. 9.

[0119] Among the signals output from the HARQ controller 30, a bufferpage select signal OBUF_PAGE[1:0] and a first buffer write enable signalOBUF0_W_EN are output to the output buffer 400 as illustrated in FIG. 5.After completion of turbo decoding, the fast turbo decoder 40 outputsdecoded data DATA[15:0] and at the same time, outputs an addressOBUF_ADDR where the decoded data is to be stored. The data output fromthe fast turbo decoder 40 is input to a demultiplexer 401. Thedemultiplexer 401 has a write enable input terminal for selecting afirst buffer OBUF#0 410 or a second buffer OBUF#1 420 and writing thedecoded data in the selected buffer. A signal input to the write enableinput terminal is a first buffer write enable signal OBUF0_W_EN. Thefirst buffer write enable signal OBUF0_W_EN has a level of ‘high’ or‘low’. For example, if the first buffer write enable signal OBUF0_W_ENin a ‘high’ state is input to the write enable input terminal of thedemultiplexer 401, the demultiplexer 401 outputs its input data to thefirst buffer 410. In contrast, if the first buffer write enable signalOBUF0_W_EN in a ‘low’ state is input to the write enable input terminalof the demultiplexer 401, the demultiplexer 401 outputs its input datato the second buffer 420.

[0120] An actual buffer of the output buffer is comprised of the firstbuffer 410 and the second buffer 420. The first buffer 410 and thesecond buffer 420 have the same size and the same internal structure. Inthe embodiment of the present invention, the first buffer 410 and thesecond buffer 420 each comprise 4 pages of PAGE#0, PAGE#1, PAGE#2 andPAGE#3, and the size of each page is 16×256. The first buffer 410 andthe second buffer 420 both have a chip select signal input terminal CSand a read/write signal input terminal R/W. In addition, the firstbuffer 410 and the second buffer 420 have a data read/write addressinput terminal ADDR_OBUF0[9:0] and a data read/write address inputterminal ADDR_OBUF1[9:0], respectively.

[0121] To the read/write signal input terminals R/W of the first buffer410 and the second buffer 420, is input the first buffer write enablesignal OBUF0_W_EN which is also input to the write enable input terminalof the demultiplexer 401. Output terminals of the first buffer 410 andthe second buffer 420 are connected to input terminals of a firstmultiplexer 402. The first multiplexer 402 selects one of outputs of thefirst buffer 410 and the second buffer 420 based on the first bufferwrite enable signal OBUF0_W_EN.

[0122] The address input terminal of the first buffer 410 is connectedto an output terminal of a second multiplexer 403, and receives aread/write address signal ADDR_OBUF0[9:0] for the first buffer 410.Similarly, the address input terminal of the second buffer 420 isconnected to an output terminal of a third multiplexer 404, and receivesa read/write address signal ADDR_OBUF1[9:0] for the second buffer 420.

[0123] The second multiplexer 403 receives a first buffer read addresssignal OBUF_RADDR[9:0] comprised of a total of 10 bits of RADDRO[9:8]and RADDRO[7:0] from the processor 50. That is, the processor 50 outputsa read address signal at once, and among the 10 bits, 2 high bitsrepresent a corresponding page of the output buffer. In addition, thesecond multiplexer 403 receives a first buffer write address signalOBUF_WADDR[9:0] comprised of WADDRO[9:8] and WADDRO[7:0] from the fastturbo decoder 40. Such signals are selectively output based on the firstbuffer write enable signal OBUF0_W_EN applied to the second multiplexer403.

[0124] The third multiplexer 404 receives a second buffer read addresssignal OBUF_RADDR[9:0] comprised of RADDR1[9:8] and RADDR1[7:0] from theprocessor 50. In addition, the third multiplexer 404 receives a secondbuffer write address signal OBUF_WADDR[9:0] comprised of WADDR1[9:8] andWADDR1[7:0] from the fast turbo decoder 40. Such signals are selectivelyoutput based on the first buffer write enable signal OBUF0_W_EN appliedto the third multiplexer 404. The third multiplexer 404 and the secondmultiplexer 403 receive the same signal. Therefore, a select signalinput terminal of one of the two multiplexers should comprise an inverseterminal. In the embodiment of the present invention, a select signalinput terminal of the third multiplexer 404 comprises an inverseterminal.

[0125] In operation, decoded data DATA[15:0] and an output bufferaddress signal OBUF_ADDR[7:0] are received from the fast turbo decoder40. A buffer page select signal OBUF_PAGE[1:0] designating a page wherethe data decoded by the fast turbo decoder 40 is stored, and a firstoutput buffer write enable signal OBUF0_W_EN are applied to the outputbuffer 400 from the output buffer controller 300 in the HARQ controller30. The decoded data DATA[15:0] is input to the demultiplexer 401, andselects the first buffer 410 or the second buffer 420 based on the firstoutput buffer write enable signal OBUF0_W_EN and outputs the decodeddata to the selected buffer.

[0126] A chip select signal CS selects the first buffer 410 or thesecond buffer 420 according to the select signal and enables theselected buffer. Based on a first output buffer write signalADDR_OBUF0[9:0] or a second output buffer write signal ADDR_OBUF1[9:0]output from the second multiplexer 403 or the third multiplexer 404, thedecoded data is written in a corresponding address of the page.

[0127] When given data is written through the above process and theprocessor 50 reads out the data, a first buffer read address signalOBUF_RADDR[9:0] is input to the second multiplexer 403 or a secondbuffer read address signal OBUF_RADDR[9:0] is input to the thirdmultiplexer 404. At this point, the first output buffer write enablesignal OBUF0_W_EN is input to the output buffer 400 from the outputbuffer controller 300. Based on this, a corresponding buffer isselected, and data is output from the selected buffer. The data outputfrom the first buffer 410 or the second buffer 420 is input to the firstmultiplexer 402, and the first multiplexer 402 selectively outputs thedecoded data based on the first output buffer write enable signalOBUF0_W_EN.

[0128]FIG. 10 is a detailed block diagram illustrating a structure of anoutput buffer controller according to an embodiment of the presentinvention. Structure and operation of the output buffer controlleraccording to the present invention will now be described with referenceto FIG. 10.

[0129] In the embodiment of the present invention, it is assumed that anEV-DV system supports 1-slot ACK/NAK_DELAY or 2-slot ACK/NAK_DELAY.Therefore, the output buffer controller 300 according to an embodimentof the present invention is designed so that the EV-DV system cansupport both 1-slot ACK/NAK_DELAY and 2-slot ACK/NAK_DELAY. In FIG. 10,a block used for 1-slot ACK/NAK_DELAY includes a page/buffer selector310, while blocks used for 2-slot ACK/NAK_DELAY include a page selector320, a buffer selector 330, and a stop position selector 340. Otherblocks 350, 360, 301, 302 and 303 are common blocks. Operation andstructure of the blocks will now be described.

[0130] First, the page/buffer selector 310 will be described. Thepage/buffer selector 310 outputs a buffer select signal and a pagesignal in order to write turbo-decoded data in an output buffer in a1-slot ACK/NAK_DELAY mode. The buffer select signal OBUF_W_EN_1S outputfrom the page/buffer selector 310 is a signal for selecting one of thefirst buffer 410 and the second buffer 420. The page select signalOBUF_PAGE_1S[1:0] output from the page/buffer selector 310 is a signalfor selecting a page of the selected buffer. In addition, thepage/buffer selector 310 generates an interrupt signal INT_TURBO_1S fortransmitting data every 5 msec. In order to generate the interruptsignal, the page/buffer selector 310 uses a system synchronizationsignal SYNC_125 as an input signal, and is cleared once duringinitialization of the fast turbo decoder 40, and thereafter,continuously operated by the SYNC_125. Detailed structure and operationof the page/buffer selector 310 will now be described with reference toFIG. 11.

[0131]FIG. 11 is a block diagram illustrating a detailed structure ofthe page/buffer selector according to an embodiment of the presentinvention. The page/buffer selector 310 receives a clear signal which isinput once during initialization of the fast turbo decoder 40. Inaddition, the page/buffer selector 310 receives the systemsynchronization signal SYNC_125. The clear signal and the systemsynchronization signal are input to a 3-bit counter 311. The 3-bitcounter 311 clears (or initializes) its count value upon receiving theclear signal, then counts the system synchronization signal received,thereafter outputs an inverted 1-slot ACK/NAK_DELAY-based buffer writeenable signal OBUF0_2_EN_1S[2] according to the count result, andoutputs a 1-slot ACK/NAK_DELAY-based buffer page select signalOBUF_PAGE_1S[1:0]. The inverted signal is converted into a normal signalby an inverter 312, and the page select signal is output directly. Thepage select signal and the system synchronization signal are input to anAND gate 313, and the AND gate 313 performs a logical AND operation onits input signals and generates a 1-slot ACK/NAK_DELAY-based interruptsignal INT_TURBO_1S.

[0132] Turning back to FIG. 10, a description will be made of the pageselector 320. As mentioned above, the page selector 320 is used in a2-slot ACK/NAK_DELAY mode. The page selector 320 generates a page selectsignal OBUF_PAGE_2S[1:0] for setting a page where turbo-decoded data isto be written when the turbo-decoded data is stored in one of the firstbuffer 410 and the second buffer 420. The page selector 320 can becomprised of a 2-bit counter. In this case, the 2-bit counter receives apacket data channel turbo decoding-done signal PDCH_TURBO_DONE. The pageselector 320 is cleared during initialization of the fast turbo decoder40, and thereafter, is cleared in synchronism with a signal INT_TURBO_2Soutput from the buffer selector 330.

[0133] Next, the buffer selector 330 will be described. The bufferselector 330 is used in the 2-slot ACK/NAK_DELAY mode. The bufferselector 330 generates a buffer select signal OBUF_W_EN_2S for selectingone of the first buffer 410 and the second buffer 420 in order to storeturbo-decoded data. Since the buffer select signal OBUF_W_EN_2S is usedas a multiplexer select signal for the output buffer 400, it has a levelof ‘high’ or ‘low’. In addition, the buffer selector 330 generates aninterrupt signal INT_TURBO_2S for transmitting data at every 5-msecboundary and its vicinity based on the 2-slow ACK/NAK_DELAY. A detailedstructure of the buffer selector 330 will now be described withreference to FIG. 12.

[0134]FIG. 12 is a block diagram illustrating a detailed structure ofthe buffer selector 330 according to an embodiment of the presentinvention. The buffer selector 330 receives 4 kinds of input signals. Adescription will be made of the 4 kinds of input signals.

[0135] (1) INT_STOP_POS[4:0]: It is a value providing a generationposition of INT_STOP. That is, this value represents a time limit whereposition setting of a turbo decoder enable signal PDCH_TURBO_EN cannotoccur, and the PDCH_TURBO_EN should always have a smaller value thanthis INT_STOP_POS. Therefore, INT_STOP_POS is used to detect a situationwhere PDCH_TURBO_EN can be no longer generated in the correspondingslot, by comparing this value with the PDCH_TURBO_EN.

[0136] (2) TURBO_EN_ACT: It is a signal indicating whether a turbodecoder enable signal PDCH_TURBO_EN is generated for one 1.25-msec slot,and has a value of ‘0’ if there is no turbo decoder enable signalPDCH_TURBO_EN within one slot.

[0137] (3) Turbo decoder enable signal (PDCH_TURBO_EN)

[0138] (4) 1-slot ACK/NAK_DELAY-based buffer page signal(OBUF_PAGE_1S[1:0]: The 1-slot ACK/NAK_DELAY-based buffer page signal isa signal generated by ANDing the system synchronization signal SYNC_125and the output signal of the 3-bit counter 311 as described inconjunction with FIG. 11. This signal is used for detecting pageswitching information. The detection information will be described indetail with reference to FIG. 12.

[0139] The 1-slot ACK/NAK_DELAY-based buffer page signalOBUF_PAGE_1S[1:0] is input to a page detector 331. The page detector 331outputs a value of ‘1’ if the 1-slot ACK/NAK_DELAY-based buffer pagesignal OBUF_PAGE_1S[1:0] indicates ‘0 page’, and otherwise, the pagedetector 331 outputs a value of ‘0’. The INT_STOP_POS[4:0] is input to athreshold comparator 332. Here, the INT_STOP_POS[4:0] is a valueindicating a time limit where position setting of the turbo decoderenable signal PDCH_TURBO_EN cannot occur, and the PDCH_TURBO_EN shouldalways have a smaller value than the INT_STOP_POS[4:0]. Therefore, theINT_STOP_POS[4:0] is a signal used to detect a situation wherePDCH_TURBO_EN can be no longer generated in the corresponding slot, bycomparing this value with the PDCH_TURBO_EN. The threshold comparator332 outputs a value of ‘1’ if an INT_STOP_POS[4:0] value is larger thana predetermined threshold M, and otherwise, the threshold comparator 332outputs a value of ‘0’. An output signal of the page selector 331 andthe turbo decoder enable signal PDCH_TURBO_EN are input to a first ANDgate 333, and the first AND gate 333 performs a logical AND operation onits two input signals. A second AND gate 334 receives an inverted valueof TURBO_EN_ACT and output values of the page detector 331 and thethreshold comparator 332, and performs a logical AND operation on itsinput values.

[0140] Output signals of the first AND gate 333 and the second AND gate334 are input to an OR gate 335, and the OR gate 335 performs a logicalOr operation on its two input signals. An output signal of the OR gate335 is divided into two signals: one of the two signals is input to apulse generator 336 and the other signal is input to a toggle unit 337.The pulse generator 336 generates one pulse signal INT_TURBO_2S based onan signal output from the OR gate 335, and the toggle unit 337 outputs a2-slot ACK/NAK_DELAY-based buffer write enable signal OBUF_W_EN_2Sdepending on an output of the OR gate 335.

[0141] Summarizing, the pulse signal INT_TURBO_2S and the 2-slotACK/NAK_DELAY-based buffer write enable signal OBUF_W_EN_2S, outputsignals of the buffer selector 330 of FIG. 12, are generated when thefollowing conditions are satisfied. First, these signals are generatedwhen ‘0 page’ is detected by the 1-slot ACK/NAK_DELAY-based buffer writeenable signal and the turbo decoder enable signal PDCH_TURBO_EN isgenerated. In this case, an output of the first AND gate 333 becomes‘1’. Second, these signals are generated when ‘0 page’ is detected bythe 1-slot ACK/NAK_DELAY-based buffer write enable signal andINT_STOP_POS[4:0] is larger than a preset threshold in a state where theturbo decoder enable signal PDCH_TURBO_EN is not generated. In thiscase, an output of the second AND gate 334 becomes ‘1’.

[0142] That is, in order to detect 5 msec, ‘0 page’ is used as anindicator, and under this condition, the buffer selector 330 determinesa report operation depending on whether the turbo decoder enable signalPDCH_TURBO_EN is generated. If the turbo decoder enable signalPDCH_TURBO_EN is generated, switchover between interrupt and buffer isperformed in an instant. However, if the turbo decoder enable signalPDCH_TURBO_EN is not generated, the buffer selector 330 waits until aposition of a threshold M (=maximum position, e.g., M=16) which is apossible maximum delay position of the turbo decoder enable signalPDCH_TURBO_EN. Thereafter, the moment the threshold is exceeded, thebuffer selector 330 switches the buffer by compulsory. Here, an eventwhere the turbo decoder enable signal PDSH_TURBO_EN is generated and anevent where the buffer selector 330 waits until the position of thethreshold, the maximum delay position, by the INT_STOP_POS[4:0], aremutually exclusive. Therefore, only one of the two events occurs at acircuit time. A TURBO_EN_ACT flag uses this principle.

[0143] The stop position selector (or INT_STOP position selector) 340provides position information of INT_STOP that can be randomly setwithin one slot. The stop position selector 340 receives a systemsynchronization signal SYNC_125, a turbo clock TURBO_CLK, and a clearsignal CLEAR. The clear signal is cleared by every systemsynchronization signal SYNC_125, and performs 31 counts in a 1.25-msecperiod. Here, 31 is a randomly given value, and this value can be can beset to a different value when a more precise PDCH_TURBO_EN gap isrequired by a designer during implementation. In addition, the stopposition selector 340 can be comprised of a counter that performs asmany counts as a predetermined number of bits, and counts the number ofbits of 0 to M in one 1.25-msec slot. Here, the INT_STOP has a value of0 to 31 that can be designated by INT_STOP_POS[4:0], and in this case, Mis a value determined by MAC. Therefore, it means that in INT_STOP_POSlarger than M, no more turbo decoding can occur. The INT_STOP_POS[4:0]signal output from the stop position selector 340 can be used by theHARQ controller 30 in setting INT_STOP to a particular position.

[0144] A flag generator 350 determines whether a turbo decoder enablesignal is generated in a slot, and outputs an active flag signalTURBO_EN_ACT of the fast turbo decoder 40. The flag generator 350receives a system clock SYNC_125 and a turbo decoder enable signalPDCH_TURBO_EN of a packet data channel. The flag generator 350 iscleared by the system clock SYNC_125, and outputs a flag signal of ‘1’if the active flag signal TURBO_EN_ACT of the fast turbo decoder 40 isgenerated even once in the 1.25-msec period. The flag generator 350 canbe comprised of a flip-flop, and receives the system clock SYNC_125 as aclear signal. If an input signal ‘1’ is received as a turbo decoderenable signal PDCH_TURBO_EN of a packet data channel, the flag generator350 outputs the input signal ‘1’ as an active flag signal TURBO_EN_ACTof the fast turbo decoder 40.

[0145] An interrupt controller 360 receives a 5-msec interrupt generatedin the 1-slotACT/NAK_DELAY and 2-slot ACK/NAK_DELAY modes, and deliversthe received interrupt to the HARQ controller 30. The interruptcontroller 360 generates an interrupt only when any encoder packetdecoded without an error exists in the output buffer (OBUF0 or OBUF1)400 that was in a write mode for 5 msec. The interrupt controller 360will now be described in detail with reference to FIG. 13.

[0146]FIG. 13 is a block diagram illustrating a detailed structure ofthe interrupt controller according to an embodiment of the presentinvention. Referring to FIG. 13, the interrupt controller 360 includestwo OR gates 361 and 362, two multiplexers 363 and 364, and one AND gate365. The first OR gate 361 receives each page status information of thefirst output buffer 410 as its input signals, and the second OR gate 362receives each page status information of the second output buffer 420 asits input signals. In the embodiment of the present invention, sinceeach output buffer is comprised of 4 pages as illustrated in FIG. 9, thefirst OR gate 361 and the second OR gate 362 each receive 4 inputsignals. The first and second output buffers 410 and 420 generate outputbuffer status signals OBUF0_STATUS and OBUF1_STATUS, respectively. Thefirst and second output buffers 410 and 420 output an ‘Empty’ signal asstatus information when there is no data. If the ‘Empty’ signal isreceived, the interrupt controller 360 does not send an interrupt signalto the HARQ controller 30 even though INT_TURBO_1S or INT_TURBO_2S isgenerated. That is, the interrupt controller 360 disables an interruptsignal INT_HOST being transmitted to the processor 50.

[0147] Output signals of the first and second OR gates 361 and 362 areinput to the first multiplexer 363, and the first multiplexer 363selects one of the output signals based on the first output buffer writeenable signal OBUF0_W_EN. Also, the second multiplexer 364 receives thestatus signals OBUF0_STATUS and OBUF1_STATUS from the first and secondoutput buffers 410 and 420, and outputs one of the two status signals asan output buffer status signal OBUF_STATUS[4N+19:0] based on the firstoutput buffer write enable signal OBUF0_W_EN. The AND gate 365,receiving an output signal of the first multiplexer 363 and an INT_TURBOsignal, ANDs the two input signals, and outputs an interrupt signalINT_HOST to the processor 50.

[0148] Through this, the HARQ controller 30 writes an EP_SIZE_TURBOvalue in this register in a manner shown in Table 2 below each time thestatus signals OBUF0_STATUS and OBUF1 ₋STATUS of the first and secondoutput buffers and the turbo decoder enable signal PDCH_TURBO_EN of apacket data channel are generated. TABLE 2 CODE 000 001 010 011 100 101110 111 EP size Empty 408 792 1560 2328 3096 3864 RVD

[0149] In addition, the interrupt controller 360 provides the processor50 with a processor interrupt signal INT_HOST and the status signalsOBUF0_STATUS and OBUF1_STATUS, set to a read mode, of the first andsecond output buffers. At this time, the interrupt controller 360delivers the output buffer status signal OBUF_STATUS[4N+19:0] outputfrom the second multiplexer 364 as well. In the output buffer statussignal OBUF_STATUS[4N+19:0], ‘N’ denotes the number of information bitsfor notifying time information of a received packet to the processor 50,and 4N bits are assigned considering that a total of 4 packets aresimultaneously transmitted to the processor 50. In addition, theinterrupt controller 360 can transmit various parameters required by anupper layer, observed in a receiver, all together. For example, theinterrupt controller 360 can transmit only the above parameters in anormal mode, and transmit various parameters observed in a receiver alltogether to an upper layer in a test mode or an observation mode.Therefore, in the present invention, parameters delivered to the upperlayer are not limited to the above-stated parameters.

[0150] The processor 50 then receives the values, determines a size ofdata stored in the output buffer set to a read mode depending on thereceived values, and reads data having a set size from a correspondingpage. Specifically describing, the data size becomes a decoded EP blocksize, a retransmission channel ID, and a system time SYS_TIME.

[0151] A size of an encoder packet stored in each page is determined bythe codes shown in Table 2. Therefore, since ‘000b’ indicates that thereis no data in a corresponding page, the processor 50 can skip thecorresponding page. The processor 50 generates a read address from theoutput buffer status signal OBUF_STATUS and each page's data size, andaccesses the output buffer using the generated read address.

[0152]FIG. 14 is a timing diagram of signals output from the outputbuffer controller in a 1-slot ACK/NAK_DELAY mode according to anembodiment of the present invention. With reference to FIG. 14, adetailed description will now be made of timings of signals output fromthe output buffer controller in the 1-slot ACK/NAK_DELAY mode accordingto the embodiment of the present invention.

[0153] As illustrated in FIG. 14, the fast turbo decoder 40 uses a turbodecoder clock TURBO_CLK as a system clock, and also uses a turbo decoderenable signal PDCH_TURBO_EN of a packet data channel as the systemclock. The turbo decoder enable signal PDCH_TURBO_EN of a packet datachannel received from the HARQ controller 30 can be continuouslygenerated every slot or discontinuously generated according to how abase station schedules the packet data channel. A relationship betweenthe turbo decoder enable signal PDCH_TURBO_EN of a packet data channeland the turbo decoding-done signal PDCH_TURBO_DONE indicating completionof a decoding operation of the fast turbo decoder 40, illustrated inFIG. 14, shows typical examples available in FIG. 8. Particularly, therelationship shows the worst case in which a new subpacket iscontinuously received every 1.25-msec slot and thus, the HARQ controller30 continuously generates the turbo decoder enable signal PDCH_TURBO_ENof a packet data channel every slot. In FIG. 14, it is assumed that onlythe double buffer structure is used in which two buffers are included,and the above-stated method of transmitting 4 decoded encoder packetsall together is not considered.

[0154] A decoding operation of the fast turbo decoder 40 is performedbetween a k^(th) turbo decoder enable signal PDCH_TURBO_EN(k) of apacket data channel and a k^(th) turbo decoding-done signalPDCH_TURBO_DONE(k) in one slot, and is not performed between the k^(th)turbo decoding-done signal PDCH_TURBO_DONE(k) and its consecutive(k+1)^(th) turbo decoder enable signal PDCH_TURBO_EN(k+1) of a packetdata channel. However, even though the decoding operation of the fastturbo decoder 40 is suspended, an operation of an output buffer in thefast turbo decoder 40 is continuously performed, and the operation canbe performed for a maximum of 2 slots (2.5 msec) from the slot where thek^(th) turbo decoder enable signal PDCH_TURBO_EN(k) of a packet datachannel is generated. That is, a double output buffer is used. It isnoted in FIG. 14 that a decoding result of a (k+1)^(th) encoder packetEP(k+1) is maintained until a (k+3)^(th) slot.

[0155] Since the fast turbo decoder 40 performs iterative decoding for aturbo decoding time, the fast turbo decoder 40, as shown in FIG. 14,iteratively performs DEC1 and DEC2, performs CRC check on every DEC2result, and reports the CRC check result to the HARQ controller 30.Here, DEC1 and DEC2 refer to a component decoder #1 and a componentdecoder #2, respectively, used in each turbo decoder. An iterationnumber of the fast turbo decoder 40 is determined depending on acondition of a received channel and a size of an encoder packet. Asillustrated in FIG. 14, the first output buffer (OBUF0) 410 and thesecond output buffer (OBUF1) 420 are subject to write enable switching,as follows.

[0156] (1) The first output buffer OUT_BUFO is provided with a writeenable signal WRITE_ENABLE when a (k+2m)^(th) turbo decoder enablesignal PDCH_TURBO_EN[k+2m] of a packet data channel is set up, wherem=0, 1, 2,

[0157] (2) The first output buffer OUT_BUFO is provided with a readenable signal READ_ENABLE when a (k+2m)^(th) turbo decoding-done signalPDCH_TURBO_DONE[k+2m] is set up, where m=0, 1, 2, . . .

[0158] (3) The second output buffer OUT_BUF1 is provided with a writeenable signal WRITE_ENABLE when a (k+2m+1)^(th) turbo decoder enablesignal PDCH_TURBO_EN[k+2m+1] of a packet data channel is set up, wherem=0, 1, 2, . . .

[0159] (4) The second output buffer OUT_BUF1 is provided with a readenable signal READ_ENABLE when a (k+2m+1)^(th) turbo decoding-donesignal PDCH_TURBO_DONE[k+2m+1] is set up, where m=0, 1, 2, . . .

[0160] Referring to FIG. 14, it is noted that decoding of a packet datachannel is performed over 3 slots from a time when the k^(th) turbodecoder enable signal PDCH_TURBO_EN[k] of a packet data channel isgenerated through a time when data transferring is completed. However,in the 1-slot ACK/NAK_DELAY mode, it is. preferable that the HARQcontroller 30 sets up the k^(th) turbo decoder enable signalPDCH_TURBO_EN[k] of a packet data channel as earliest as possible afterthe k^(th) turbo decoding-done signal PDCH_TURBO_DONE [k] is set up.Therefore, a gap between the two signals is not long. As a result, inFIG. 14, even though data transmission for EP[k] is suspended at theslot boundary and its environs, a data transferring time is notconsiderably affected.

[0161]FIG. 15 is a timing diagram illustrating an example in which thesum of a decoding time of a fast turbo decoder and a data transferringtime is limited to 2.5 msec in a 1-slot ACK/NAK_DELAY mode according toan embodiment of the present invention. With reference to FIG. 15, adetailed description will now be made of the case in which the sum of adecoding time of the fast turbo decoder 40 and a data transferring timeis limited not to exceed 2.5 msec in a 1-slot ACK/NAK_DELAY modeaccording to a preferred embodiment of the present invention.

[0162] The reason for limiting the sum of a decoding time of the fastturbo decoder 40 and a data transferring time not to exceed 2.5 msec isto simplify control of the output buffer. In the 1-slot ACK/NAK_DELAYmode, in most cases, it is possible to assign the longest decoding timeby placing the turbo decoder enable signal PDCH_TURBO_EN of a packetdata channel as close as possible to the slot boundary. Commonly, thedata transferring time reduced in this manner is shorter than‘t_demod+t_GAP’. Since the ‘t_demod’ is a very small value, thedifference is not considerable. Therefore, in the 1-slot ACK/NAK_DELAYmode, all operations, including PDCH demodulation, demapping, decodingby the fast turbo decoder 40 and data transferring, are performed within2 slots (2.5 msec).

[0163]FIGS. 16 and 17 are timing diagrams of an output buffer in a fastturbo decoder in a 2-slot ACK/NAK_DELAY mode according to an embodimentof the present invention. With reference to FIGS. 16 and 17, a detaileddescription will now be made of an operation of an output buffer in afast turbo decoder in the 2-slot ACK/NAK_DELAY mode according to anembodiment of the present invention.

[0164] As illustrated in FIG. 16, an output buffer in the fast turbodecoder 40 uses a turbo decoding clock TURBO_CLK as a system clock, andalso uses the turbo decoder enable signal PDCH_TURBO_EN of a packet datachannel as the system clock. Unlike in the 1-slot ACK/NAK_DELAY mode, inthe 2-slot ACK/NAK_DELAY mode, read/write switching of an output bufferoccurs at irregular intervals. It can be noted that read/write switchingis irregular according to generation positions of the turbo decoderenable signal PDCH_TURBO_EN of a packet data channel is and the turbodecoding-done signal. As illustrated in FIG. 16, the fast turbo decoder40 can maintain decoding of a k^(th) encoder packet until a time atwhich a (k+1)^(th) turbo decoder enable signal PDCH_TURBO_EN[k+1] of apacket data channel is generated. Therefore, a read/write switching timeof the output buffer is also determined by the turbo decoder enablesignal PDCH_TURBO_EN of a packet data channel. In addition, it can benoted from FIG. 16 that decoding of a packet data channel and datatransferring are performed over 3 slots from a time when the k^(th)turbo decoder enable signal PDCH_TURBO_EN[k] of a packet data channel isgenerated through a time when data transferring is completed. Asillustrated in FIG. 16, a data transferring time is longer than or equalto a minimum of 1.25 msec.

[0165]FIG. 17 illustrates an extreme example of data transferring anddecoding by the fast turbo decoder 40 according to an embodiment of thepresent invention. As illustrated in FIG. 17, when a (k+1)^(th) turbodecoder enable signal PDCH_TURBO_EN[k+1] of a packet data channel isgenerated at a rear boundary of a slot and a (k+2)^(th) turbo decoderenable signal PDCH_TURBO_EN[k+2] of a packet data channel is generatedat a rear boundary of the nest slot, PDCH decoding and data transferringcan occur over almost 3 slots.

[0166]FIG. 18 is a timing diagram illustrating examples of controltimings of an output buffer and operations of a fast turbo decoder in a1-slot ACK/NAK_DELAY mode and a 2-slot ACK/NAK_DELAY mode according toan embodiment of the present invention. With reference to FIG. 18, adetailed description will now be made of typical output buffer controltimings and fast turbo decoder's operations in a 1-slot ACK/NAK_DELAYmode and a 2-slot ACK/NAK_DELAY mode according to an embodiment of thepresent invention.

[0167] Since the output buffer 300 supports both the 1-slotACK/NAK_DELAY and 2-slot ACK/NAK_DELAY modes, it should be able toindependently operate for each mode. First, an operation in the 1-slotACK/NAK_DELAY mode will be described. It can be noted from FIG. 18 thatin the 1-slot ACK/NAK_DELAY mode, selection of output buffers OBUF0 andOBUF1 and page selection in each output buffer are performed on aregular basis. In addition, the processor 50 supports a method ofgathering 4 decoded encoder packets and transmitting the gatheredencoder packets every 5 msec, in order to reduce an interrupt load.Major operations in the 1-slot ACK/NAK_DELAY mode will be describedbelow.

[0168] (1) Switching of the first output buffer (OBUF0) 410 and theoutput buffer (OBUF1) 420 and page switching in a particular outputbuffer are performed by 1-slot buffer page select signalsOBUF_PAGE_1S[2] and OBUF_PAGE_1S[1:0] which are signals determined by avalue of a counter that operates depending on a system time SYNC_125(1.25-msec slot SYNC), irrespective of a generation position of a turbodecoder enable signal PDCH_TURBO_EN of a packet data channel in oneslot.

[0169] (2) The first output buffer (OBUF0) 410 and the second outputbuffer (OBUF1) 420 are each divided into of 4 pages by theOBUF_PAGE_1S[1:0]. In addition, page switching in each output bufferoccurs on a regular basis by a value between 0 and 3 periodicallygenerated by a 3-it counter.

[0170] (3) When a turbo decoder enable signal PDCH_TURBO_EN of a packetdata channel is generated, the fast turbo decoder 40 stores decoded datain a corresponding page of the output buffer according to pageinformation of the output buffer assigned by the HARQ controller 30.

[0171] (4) In order to send the processor 50 an interrupt for datatransmission, the HARQ controller 30 generates a turbo interrupt signalINT_TURBO every 5 msec, and this signal is determined by a value of acounter that operates according to a system time SYNC_125 (1.25-msecslot SYNC).

[0172] (5) Switching of read/write modes between the first output buffer(OBUF0) 410 and the second output buffer (OBUF1) 420 is determined by aturbo interrupt signal INT_TURBO.

[0173] (6) Read/write operations of the first output buffer (OBUF0) 410and the second output buffer (OBUF1) 420 are mutually exclusive.

[0174] (7) When 4 encoder packets are continuously transmitted, all datais stored in page#0, page#1, page#2 and page#3 of the output buffer. Incontrast, when only several encoder packets are transmitted and no datais transmitted in the remaining period, data is stored only in a slotwhere a turbo decoder enable signal PDCH_TURBO_EN of a packet datachannel is generated among the 4 pages of the output buffer. However,switching between read/write modes must be performed according to theturbo interrupt signal INT_TURBO.

[0175] Next, an operation in the 2-slot ACK/NAK_DELAY mode will bedescribed. It can be noted from FIG. 18 that in the 2-slot ACK/NAK_DELAYmode, selection of output buffers OBUF0 and OBUF1 and page selection ineach output buffer are performed on an irregular basis. This is becausethe fast turbo decoder 40 performs decoding, crossing over the slotboundary. Like in the 1-slot ACK/NAK_DELAY mode, the processor 50supports a method of gathering 4 decoded encoder packets andtransmitting the gathered encoder packets at every 5-msec boundary andits environs, in order to reduce an interrupt load. Major operations inthe 2-slot ACK/NAK_DELAY mode are summarized below.

[0176] (1) Buffer switching of the first output buffer (OBUF0) 410 andthe output buffer (OBUF1) 420 and page switching in a particular outputbuffer occur in association with a generation position of a turbodecoder enable signal PDCH_TURBO_EN of a packet data channel in one slotand a generation position of a turbo decoding-done signalPDCH_TURBO_DONE. In addition, its value is determined considering theOBUF_PAGE_1S[1:0] which is a signal determined by a value of a counterthat operates according to a system time SYNC_125 (1.25-msec slot SYNC).

[0177] (2) The first output buffer (OBUF0) 410 and the second outputbuffer (OBUF1) 420 are each divided into of 4 pages by a 2-slot outputbuffer select signal OBUF_PAGE_2S[1:0] and this value is updated bygeneration of a turbo decoding-done signal PDCH_TURBO_DONE. That is,regarding page switching in each output buffer, a page of the outputbuffer is selected by a value of a counter up-counted by a turbodecoding-done signal PDCH_TURBO_DONE starting at a page #0 in the 2-slotoutput buffer select signal OBUF_PAGE_2S[1:0] cleared by a turbointerrupt INT_TURBO.

[0178] (3) When a turbo decoder enable signal PDCH_TURBO_EN of a packetdata channel is generated, the fast turbo decoder 40 stores decoded datain a corresponding page of the output buffer according to pageinformation of the output buffer assigned by the HARQ controller 30.Pages of the output buffer cannot be switched until a turbodecoding-done signal is generated. Therefore, in some cases, one pagemay be continued for 4 slots. This is the most significant differencefrom the 1-slot ACK/NAK_DELAY.

[0179] (4) In order to send the processor 50 an interrupt for datatransmission, the HARQ controller 30 generates a turbo interrupt signalINT_TURBO every 5-msec boundary and its vicinity, and this signal isdetermined depending on page#0 information generated from theOBUF_PAGE_1S[1:0] for the 1-slot ACK/NAK_DELAY, whether a turbo decoderenable signal PDCH_TURBO_EN of a packet data channel is generated fromthe page#0, and whether a turbo decoder enable signal PDCH_TURBO_EN of apacket data channel is generated in 4 previous slots.

[0180] (5) Switching of read/write modes between the first output buffer(OBUF0) 410 and the second output buffer (OBUF1) 420 is determined by aturbo interrupt signal INT_TURBO.

[0181] (6) Read/write operations of the first output buffer (OBUF0) 410and the second output buffer (OBUF1) 420 are mutually exclusive.

[0182] (7) When 4 encoder packets are continuously transmitted, all datais stored in page#0, page#1, page#2 and page#3 of the output buffer. Incontrast, when only several encoder packets are transmitted and no datais transmitted in the remaining period, data is stored only in a slotwhere a turbo decoder enable signal PDCH_TURBO_EN of a packet datachannel is generated among the 4 pages of the output buffer. However,switching between read/write modes must be performed according to theturbo interrupt signal INT_TURBO.

[0183] In the 2-slot ACK/NAK_DELAY mode, as illustrated in FIG. 18,actual switching of the read/write modes of the first output buffer 410and the second output buffer 420 should be independently performed by aturbo decoder enable signal PDCH_TURBO_EN of a packet data channel and aturbo decoding-done signal PDCH_TURBO_DONE. However, when the fast turbodecoder 40 has already completed decoding in a previous slot, it ispreferable to generate the turbo decode enable signal PDCH_TURBO_EN of apacket data channel as early as possible. Since a time differencebetween these two cases is very slight, switching of read/write modes isdetermined using the turbo decoder enable signal PDCH_TURBO_EN of apacket data channel.

[0184]FIG. 19 is a diagram illustrating operational timing between theprocessor, the HARQ controller and the fast turbo decoder in a 1-slotACK/NAK_DELAY mode according to an embodiment of the present invention.With reference to FIG. 19, a detailed description will now be made ofoperational timings between the processor, the HARQ controller and thefast turbo decoder in the 1-slot ACK/NAK_DELAY mode according to theembodiment of the present invention.

[0185] First, operation in the 1-slot ACK/NAK_DELAY mode will bedescribed. In the 1-slot ACK/NAK_DELAY mode, the HARQ controller 30, asstated above, periodically provides a 1-slot output buffer write enablesignal OBUF0_W_EN_1S for selecting an output buffer OBUF0 or OBUF1 forwriting, and the signal OBUF_PAGE_1S[1:0] for selecting a page from theselected output buffer. In addition, the turbo decoding-done signalPDCH_TURBO_DONE must be generated in the slot where the turbo decoderenable signal PDCH_TURBO_EN of a packet data channel is generated. Thefast turbo decoder 40 performs a decoding operation in a period betweenthe turbo decoder enable signal PDCH_TURBO_EN and the turbodecoding-done signal PDCH_TURBO_DONE. The HARQ controller 30 writes avalue of a turbo decoding signal EP_SIZE_TURBO determined by a size ofthe encoder packet in this register, each time the turbo decoder enablesignal PDCH_TURBO_EN of a packet data channel is generated in additionto a first output buffer status signal OBUF0_STATUS and a second outputbuffer status signal OBUF1_STATUS. The writing is performed using codesin Table 2. Switching of read/write modes of the first and second outputbuffers OBUF0 and OBUF1 is performed by a 1-slot turbo interrupt signalINT_TURBO_1S that is generated every 5 msec, and data transferring canbe performed for 5 msec. Information on an output buffer statusOBUF_STATUS, as illustrated in FIG. 19, is delivered from the HARQcontroller 30 to the fast turbo decoder 50 when a 1-slot turbo interruptsignal INT_TURBO_1S is generated, and thereafter, all status registersof the output buffer switched to a write mode are cleared. In addition,an active flag of a turbo decoder enable signal PDCH_TURBO_EN of apacket data channel is cleared every 1.25 msec.

[0186] If a turbo decoder enable signal PDCH_TURBO_EN of a packet datachannel is generated as described in conjunction with FIG. 10, an activeflag of the turbo decoder enable signal PDCH_TURBO_EN of a packet datachannel is switched to ‘1’ in status, and is cleared again by a systemtime signal SYNC_125 at the slot boundary. If a turbo decoding-donesignal PDCH_TURBO_DONE is set up and a packet data channel has a bad CRCor the HARQ controller 30 sets an intentional STOP (INT_STOP), then theHARQ controller 30 sets ‘Empty (=000b)’ in an output buffer statussignal OBUF_STATUS0 (or OBUF_STATUS1) corresponding to a page of acurrent write output buffer when the packet data channel has a bad CRCas a result of CRC check on the packet data channel. The processor 50then can skip this point without reading data. If there is no data inother pages except the bad-CRC page in the first and second outputbuffers OBUF0 and OBUF1, a processor interrupt signal INT_HOST is notgenerated. In addition, PDCH_TURBO_DONE or INT_STOP is used as aPAGE_SELECTOR (2 ACK_TIME) input signal considering the case where theHARQ controller 30 sets a stop interrupt signal INT_STOP. That is, evenwhen the stop interrupt signal INT_STOP is generated, the processor 50performs page switching considering the INT_STOP as a turbodecoding-done signal PDCH_TURBO_DONE due to ‘CRC Bad’. Information onthe page where a stop interrupt signal INT_STOP is generated is heldbecause CRC check is performed after the stop interrupt signal INT_STOPand at this time, ‘CRC Good’ can occur.

[0187]FIG. 20 is a diagram illustrating operational timing between theprocessor, the HARQ controller and the fast turbo decoder in a 2-slotACK/NAK_DELAY mode according to an embodiment of the present invention.With reference to FIG. 20, a detailed description will now be made ofoperational timings between the processor, the HARQ controller and thefast turbo decoder in the 2-slot ACK/NAK_DELAY mode according to theembodiment of the present invention.

[0188] In the 2-slot ACK/NAK_DELAY mode, the HARQ controller 30, asstated above, non-periodically provides a 2-slot first output bufferwrite enable signal OBUF0_W_EN_2S for selecting an output buffer OBUF0or OBUF1 for writing, and a 2-slot output buffer page signalOBUF_PAGE_2S[1:0] for selecting a page from the selected output buffer.In addition, the HARQ controller 30 non-periodically generates a 2-slotturbo interrupt signal INT_TURBO_2S for data transmission every 5 msec.A turbo decoder enable signal PDCH_TURBO_EN of a packet data channel canbe generated in a particular position after a demodulation-done signalPDCH_DEMOD_DONE is generated by the AHRQ controller 30. In addition,generation of a turbo decoding-done signal PDCH_TURBO_DONE can bedelayed until the next slot of a slot where the turbo decoder enablesignal PDCH_TURBO_EN of a packet data channel is generated. The fastturbo decoder 40 performs a decoding operation in a period between theturbo decoder enable signal PDCH_TURBO_EN and the turbo decoding-donesignal PDCH_TURBO_DONE. In addition, the HARQ controller 30 writes avalue of a turbo decoding signal EP_SIZE_TURBO determined by a size ofthe encoder packet in this register, each time the turbo decoder enablesignal PDCH_TURBO_EN of a packet data channel is generated in additionto a first output buffer status signal OBUF0_STATUS and a second outputbuffer status signal OBUF1_STATUS. The writing in the register isperformed using codes in Table 2. Switching of read/write modes of thefirst and second output buffers OBUF0 and OBUF1 is performed by a 2-slotturbo interrupt signal INT_TURBO_2S that is generated every 5 msec, anddata transferring can be performed for 5 msec.

[0189] Information on an output buffer status OBUF_STATUS, asillustrated in FIG. 20, is delivered from the HARQ controller 30 to thefast turbo decoder 50 when a 2-slot turbo interrupt signal INT_TURBO_2Sis generated, and thereafter, all status registers of the output bufferswitched to a write mode are cleared. In addition, an active flag of aturbo decoder enable signal PDCH_TURBO_EN of a packet data channel iscleared every 1.25 msec.

[0190] If a turbo decoder enable signal PDCH_TURBO_EN of a packet datachannel is generated within one slot as described in conjunction withFIG. 10, an active flag of the turbo decoder enable signal PDCH_TURBO_ENof a packet data channel is switched to ‘1’ in status, and is clearedagain by a system time signal SYNC_125 at the slot boundary. If a turbodecoding-done signal PDCH_TURBO_DONE is set up and a packet data channelhas a bad CRC or the HARQ controller 30 sets an intentional STOP(INT_STOP), then the HARQ controller 30 sets ‘Empty (=000b)’ in anoutput buffer status signal OBUF_STATUS0 (or OBUF_STATUS1) correspondingto a page of a current write output buffer when the packet data channelhas a bad CRC as a result of CRC check on the packet data channel. Theprocessor 50 then can skip this point without reading data. If there isno data in other pages except the bad-CRC page in the first and secondoutput buffers OBUF0 and OBUF1, a processor interrupt signal INT_HOST isnot generated. In addition, the turbo decoding-done signalPDCH_TURBO_DONE or the stop interrupt signal INT_STOP is used as aPAGE_SELECTOR (2 ACK_TIME) input signal considering the case where theHARQ controller 30 sets a stop interrupt signal INT_STOP. That is, evenwhen the stop interrupt signal INT_STOP is generated, the processor 50performs page switching considering the INT_STOP as a turbodecoding-done signal PDCH_TURBO_DONE due to ‘CRC Bad’. Information onthe page where a stop interrupt signal INT_STOP is generated is heldbecause CRC check is performed after the stop interrupt signal INT_STOPand at this time, ‘CRC Good’ can occur. As shown in FIG. 20, unlikeOBUF0_PAGE_1S[1:0], OBUF0_PAGE_2S[1:0] can be held instead of beingswitched, crossing over the slot boundary, and it can be maintained withthe same value for a maximum of 4 slots.

[0191] As illustrated in FIG. 20, a 2-slot turbo interrupt signalINT_TURBO_2S is generated by compulsory when TURBO_EN_POS[3:0] currentlyobserved by the HARQ controller 30 exceeds a threshold M of a turbodecoder enable signal PDCH_TURBO_EN of a packet data channel even thoughthe turbo decoder enable signal PDCH_TURBO_EN of a packet data channelis not generated like in a 5^(th) slot, even in other cases except thecase where the turbo decoder enable signal PDCH_TURBO_EN of a packetdata channel is generated in a page#0 generated by the OBUF_PAGE_1S[1:0]like in the first slot. This is because the first output buffer 410 andthe second output buffer 420 should be switched every 5 msec. Of course,when there is no encoder packet decoded in 4 previous slots, the 2-slotturbo interrupt signal INT_TURBO_2S is disabled by the interruptgenerator 360 described in conjunction with FIG. 10, so no interrupt ispractically generated to the processor 50.

[0192]FIG. 21 is a flowchart illustrating an entire control operationperformed by the output buffer controller according to an embodiment ofthe present invention. With reference to FIG. 21, a detailed descriptionwill now be made of a control operation performed by the output buffercontroller according to the embodiment of the present invention.

[0193] First, an initialization operation of the output buffercontroller 300 will be described. The output buffer controller 300performs an initial state in step 500. In the initial state, the outputbuffer controller 300 performs parameter initialization and outputbuffer initialization, sets an initial value of a counter to ‘0’, andsets a maximum value of the counter to a predetermined value CM. Here,CM denotes a particular constant determined by a designer. Theinitialization operation corresponds to a process of initializingparameters of an address generator. Thereafter, the output buffercontroller 300 determines in step 502 whether ACK_DELAY is 1 slot. IfACK_DELAY is 1 slot, the output buffer controller 300 proceeds to step504. Otherwise if ACK_DELAY is 2 slots, the output buffer controller 300proceeds to step 600. In step 504, the output buffer controller 300selects an output buffer address generator based on 1-slot ACK_DELAY,and then proceeds to step 602. The output buffer controller 300 performssetting based on 1-slot or 2-slot ACK_DELAY because the 1x EV-DV systemis given a variable decoding time. Therefore, since an output bufferaddress generator is changed according to ACK_DELAY provided in thesystem, this must be determined in advance.

[0194] After the initialization, the output buffer controller 300performs the process of steps 600 to 628. A detailed description willnow be made of the process of steps 600 to 628 performed by the outputbuffer controller 300.

[0195] In step 600, the output buffer controller 300 selects a 2-slotACK_DELAY-based output buffer address generator based, and then proceedsto step 602. After selecting an output buffer address generator based on1-slot or 2-slot ACK_DELAY, the output buffer controller 300 increases acount value by 1 instep 602, and then proceeds to step 604. The outputbuffer controller 300 determines in step 604 whether channel decoding isrequired due to reception of a new packet. If no packet is received froma receiver at a current slot boundary, the output buffer controller 300should wait until the next slot boundary. Particularly, in the case of2-slot ACK_DELAY, since channel decoding can be performed a maximum oftwo times in one slot, another packet can be received for channeldecoding before the slot boundary. Therefore, a process of determiningwhether a current timing is a slot boundary and waiting a packet to bereceived if no packet is received should be performed. If it isdetermined in step 604 that a new packet has been received, the outputbuffer controller 300 proceeds to step 608. Otherwise, the output buffercontroller 300 proceeds to step 606 and determines whether a currenttiming is the next slot boundary. If it is determined in step 606 thatthe current timing is the next slot boundary, the output buffercontroller 300 returns to step 602 where it increases the count value by1, and then performs the step 604 again. However, if it is determined instep 606 that the current timing is not the next slot boundary, theoutput buffer controller 300 returns to step 604.

[0196] In step 608, the output buffer controller 300 calculates anoutput buffer decision parameter. The output buffer decision parameteris a parameter value to be used in the fast turbo decoder 40 and theoutput buffer controller 300. After the parameter calculation, theoutput buffer controller 300 transmits in step 610 the output bufferdecision parameter to the fast turbo decoder 40 and at the same time,stores information related to reception data to be delivered to theprocessor 50. Thereafter, in step 612, the output buffer controller 300sends a decoding command to the fast turbo decoder 40. That is, ifawaited packet data is received from the receiver, the output buffercontroller 300 must generate information for decoding the receivedpacket, generate information on a storage position an output buffer toselect one of double output buffers, select a page of the selectedoutput buffer, and deliver information related to read/write modesetting to the fast turbo decoder 40 in advance, or deliver theinformation together with a decoding start signal. Through this, thefast turbo decoder 40 performs a turbo decoding process. In step 614,the output buffer controller 300 waits for turbo decoding of the fastturbo decoder 40 to be completed. In step 615, the output buffercontroller 300 determines whether the turbo decoding is completed. Ifthe turbo decoding is completed, the output buffer controller 300proceeds to step 616, and otherwise, returns to step 614.

[0197] In step 616, the output buffer controller 300 determines whethera storage time of the output buffer has passed. If it is determined instep 616 that a storage time of the output buffer has passed, the outputbuffer controller 300 proceeds to step 618, and if a storage time of theoutput buffer has not passed, the output buffer controller 300 returnsto step 606. Upon receiving a turbo decoding-done signal PDCH_TURBO_DONEof a packet data channel, the output buffer controller 300 determineswhether a data storage time of the output buffer has passed the maximumstorage time. If it's time to shift data accumulated so far to theprocessor 50, the output buffer controller 300 delivers information onthe packets stored in the output buffer 400 and information on a storageposition of the output buffer to the processor in advance, or deliversthe information together with an interrupt. The maximum storage time isdetermined through a comparison between CNT and CNT_MAX, and this can bedefined as CNT_MAX.

[0198] In step 618, the output buffer controller 300 sends the processor50 an interrupt for data transmission. Thereafter, in step 620, theprocessor 50 reads a parameter related to an output buffer, stored inthe output buffer controller 300, and at the same time, accesses theoutput buffer 400. At this time, the output buffer controller 300 holdsan idle state for an access to the processor 50. In step 622, theprocessor 50 reads data of a decoded encoder packet stored in theaccessed output buffer 400. Even in this case, the output buffercontroller 300 holds the idle state. In step 624, the output buffercontroller 300 determines whether data transmission from the outputbuffer 400 to the processor 50 is completed. If data transmission fromthe output buffer 400 to the processor 50 is completed, the outputbuffer controller 300 proceeds to step 626, and otherwise, the outputbuffer controller 300 holds the idle state until the processor 50 readsthe data. In FIG. 21, steps 620 and 622 are provided to show anoperation of the processor 50 as an example. Actually, the output buffercontroller 300 holds the idle state at this time.

[0199] In step 626, the output buffer controller 300 initializes aparameter related to a read output buffer, initializes parametersdelivered from the output buffer controller 300 to the processor 50, andinitializes an interrupt signal. Thereafter, in step 628, the outputbuffer controller 300 sets the count value to ‘0’, and then returns tostep 606.

[0200] Through this process, the output buffer controller 300 can storedecoded data and send the stored data to the processor 50.

[0201]FIG. 22 is a block diagram illustrating a mobile station includingan output buffer controller according to an embodiment of the presentinvention. With reference to FIG. 22, a detailed description will now bemade of a structure and operation of a mobile station receiver includingthe output buffer controller 300 according to an embodiment of thepresent invention.

[0202] A radio frequency (RF) signal transmitted from a transmitter of abase station is received via an antenna of the mobile station, and theninput to an RF section 701. The RF section 701 converts the RF signalreceived from the antenna into an intermediate frequency (IF) signal,and then converts the IF signal into a baseband signal. The analogbaseband signal is converted into a digital signal through a basebandanalog processor (BBA) 703.

[0203] The digital signal is input to a baseband interface 711 in amodem 710. The baseband interface 711 separates the digital signal intotraffic data and control data. The separated traffic data is stored in aparticular area of an input buffer 713, while the separated control datais input to an output buffer controller 300. The control informationinput to the output buffer controller 300 is used as fundamental databased on which the output buffer controller 300 operates.

[0204] The traffic data stored in the input buffer 713 is input to aturbo decoder 40. Before the turbo decoder 40 performs turbo decoding,the output buffer controller 300 outputs information related to a writeaddress where decoded data from the turbo decoder 40 is to be written.After completion of decoding, the turbo decoder 40 stores decoded datain a predetermined area of an output buffer 400 depending on the writeaddress information from the control of the output buffer controller. Inaddition, the turbo decoder 40 provides the output buffer controller 300with a decoding-done signal and decoding result information.

[0205] The output buffer controller 300 checks whether a predeterminedinterrupt condition is satisfied, based on the decoding-done signal anddecoding result information received from the turbo decoder 40 for apredetermined time. Only when the interrupt condition is satisfied, theoutput buffer controller 300 generates an interrupt signal instructing ahost (or processor) 50 to read data from the output buffer 400. At thesame time, the output buffer controller 300 provides the host 50 withinformation related to a read address where data is to be read out fromthe output buffer 400.

[0206] Upon receiving the interrupt signal and the read addressinformation, the host 50 calculates a read address of the output buffer400 based on the read address information, and then reads decoded datastored in the read address of the output buffer 400.

[0207] As can be appreciated from the foregoing description, theembodiment of the present invention can deliver decoded data withoutincreasing a load on a processor irrespective of ACK_DELAY=1 orACK_DELAY=2 in an HARQ mobile communication system. In addition, theembodiment of the present invention can secure a decoding time of a fastturbo decoder, prevent wrong error detection due to discontinuity ofHARQ-based retransmission packet data, and enable fast response.

[0208] While the invention has been shown and described with referenceto a certain embodiment thereof, it will be understood by those skilledin the art that various changes in form and details may be made thereinwithout departing from the spirit and scope of the invention as definedby the appended claims.

What is claimed is:
 1. A mobile station apparatus for receiving packetdata, decoding the received packet data and delivering the decodedpacket data to an upper layer in a mobile communication system, theapparatus comprising: a turbo decoder for decoding the packet data; abuffer for storing the decoded packet data, and outputting packet dataupon receiving a read request; a buffer controller for receiving thedecoding done signal from the turbo decoder, and generating an interruptsignal and a read address for reading data stored in the buffer; and aprocessor for reading data stored in the buffer according to the readaddress upon receiving the interrupt signal from the buffer controller.2. The mobile station apparatus of claim 1, wherein the buffer isdualized to store the decoded data; wherein each of the dualized buffersis divided into several areas having a specified size and the decodeddata is stored in the divided areas.
 3. The mobile station apparatus ofclaim 1, wherein the read address includes an area information andaddress information of the buffer where the decoded data is stored. 4.The mobile station apparatus of claim 1, wherein the buffer controllercomprises: a page buffer selector for receiving a system time signal ofa receiver, selecting one of the dualized buffers according to a 1-slotdelay response mode determined from the system time, and determining agiven page of the selected buffer; a stop position selector forreceiving the system time signal and a decoding clock, and generating astop position signal that can be randomly set in one slot; a flaggenerator being cleared according to the system time of the receiver,for outputting a flag according to a turbo decoder enable signal of thepacket data; a buffer selector for receiving a signal of the flaggenerator, an output signal of the stop position selector, and the turbodecoder enable signal, and selecting one of the dualized areas accordingto a 2-slot delay response mode; a page selector for selecting a page ofthe selected area according to the 2-slot delay response mode; and aninterrupt controller for generating an interrupt signal by receivingsignals from the page buffer selector, the buffer selector and the pageselector, and buffer status signals from the dualized area buffer. 5.The mobile station apparatus of claim 1, wherein the buffer controlleris included in a Hybrid Automatic Repeat Request (HARQ) controllerlocated in a physical layer.
 6. The mobile station apparatus of claim 1,wherein the decoded data information includes at least one of errorinformation of the decoded data, status information of the decoder, anddecoding-done information.
 7. The mobile station apparatus of claim 1,wherein the buffer controller receives the system time signal,determines an ACK/NACK delay response mode depending on the receivedsystem time signal, and selecting one of the dualized the bufferaccording to the determined delay response mode.
 8. The mobile stationapparatus of claim 1, wherein the buffer controller determines whetherthere is any decoded data in the buffer, and generates no interruptsignal when there is no decoded data in the buffer.
 9. The mobilestation apparatus of claim 1, wherein the buffer controller generates aninterrupt signal and a read address for data reading, when at least twothe decoding done signals are received.
 10. The mobile station apparatusof claim 1, wherein the buffer controller generates the interrupt signalevery 5 msec.
 11. The mobile station apparatus of claim 1, wherein thebuffer controller generates the interrupt signal according to a load onthe processor.
 12. The mobile station apparatus of claim 1, whereinafter completion of decoding, the turbo decoder provides the buffer withthe decoded data and a buffer address signal based on which the decodeddata is to be written.
 13. A method for delivering decoded data to anupper layer in a mobile station apparatus including a decoder fordecoding received packet data, the method comprising the steps of: (a)receiving the decoded data from the decoder; (b) generating an interruptsignal and a buffer read address for delivering the decoded data to theupper layer if a predetermined time has passed; and (c) transmitting thedecoded data from the buffer to the upper layer based on the interruptsignal and the buffer read address generated.
 14. The method of claim13, wherein the step (b) comprises the steps of: receiving a system timesignal, and determining an ACK/NACK delay response mode depending on thereceived system time signal; and selecting one of the dualized buffersaccording to the determined delay response mode.
 15. The method of claim13, further comprising the step of receiving a decoding-done signalafter the decoder completes decoding of the high-rate packet data. 16.The method of claim 13, wherein the decoded data information includes atleast one of error information of the decoded data, status informationof the decoder, and decoding-done information.
 17. The method of claim13, wherein the predetermined time is 5 msec.
 18. The method of claim13, wherein the interrupt signal and the data read information are notgenerated when there is no decoded packet data for a predetermined time.19. A method for delivering decoded data to an upper layer in a mobilestation apparatus including a decoder for decoding received packet data,the method comprising the steps of: receiving the decoded data from thedecoder; generating an interrupt signal and a buffer read address fordelivering the decoded data to the upper layer if a predetermined numberof data blocks are decoded by the decoder and stored in the outputbuffer; and transmitting the decoded data to the upper layer based onthe interrupt signal and the buffer address generated.
 20. The method ofclaim 19, wherein the buffer information includes information on an areaand an address of the buffer, where the decoded data is stored.
 21. Themethod of claim 19, further comprising the steps of: if no packet datais decoded over the packet data channel within a predetermined time, notgenerating an interrupt signal.
 22. The method of claim 21, wherein thepredetermined time is 5 msec.
 23. The method of claim 19, wherein thepredetermined number is two or above.
 24. A mobile station apparatus forreceiving high-rate packet data, decoding the received packet data anddelivering the decoded packet data to an upper layer in a mobilecommunication system, the apparatus comprising: an antenna for receivinga high-rate radio frequency (RF) encoder packet transmitted from atransmitter of a base station; an RF section for converting thehigh-rate RF encoder packet received from the antenna into a basebandsignal; an analog-to-digital (A/D) conversion section for converting ananalog signal from the RF section into a digital signal; a turbo decoderfor decoding the A/D-converted high-rate encoder packet data; a bufferfor storing the decoded packet data, and outputting packet data uponreceiving a read request; a buffer controller for receiving the decodeddata from the turbo decoder, and generating an interrupt signal and aread address for reading data stored in the buffer; and a processor forreading data stored in the buffer according to the read address uponreceiving the interrupt signal from the buffer controller.
 25. Themobile station apparatus of claim 24, further comprising: a basebandinterface for receiving a signal from the A/D conversion section andseparating the received signal into a control signal and high-ratepacket data; and an input buffer for temporarily storing the high-ratepacket data output from the baseband interface before decoding.
 26. Amethod for receiving high-rate packet data, decoding the received packetdata and delivering the decoded packet data to an upper layer in amobile communication system, the method comprising the steps of:receiving a high-rate radio frequency (RF) encoder packet transmittedfrom a transmitter of a base station; converting the received high-rateRF encoder packet into a baseband signal; analog-to-digital (A/D)converting the analog baseband signal into a digital signal; decodingthe A/D-converted high-rate encoder packet data, and storing the decodedpacket data; generating an interrupt signal and a read address forreading the stored data, when decoding is completed at least two times;and reading the decoded data stored in the read address in response tothe interrupt signal.